Kartik Ganapathi | University of California, Berkeley (original) (raw)

Papers by Kartik Ganapathi

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices ha... more Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance 1-8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied 7,9,10 : such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored 9,11-13-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/ SiO 2 substrates. As a parallel with silicon-on-insulator (SOI) technology 14 , we use 'XOI' to represent our compound semiconductoron-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/ dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO x layer (1 nm thick). The fabricated field-effect transistors exhibit a peak transconductance of 1.6 mS mm 21 at a drain-source voltage of 0.5 V, with an on/off current ratio of greater than 10,000. Epitaxial lift-off and transfer of crystalline microstructures to various support substrates has been shown to be a versatile technique for applications ranging from optoelectronics to large-area electronics 15-18. Specifically, high-performance, mechanically flexible macro-electronics and photovoltaics have been demonstrated on plastic, rubber and glass substrates by this method 19-21. Here we use a modified epitaxial transfer scheme for integrating ultrathin InAs layers (with nanometre-scale thicknesses) on Si/SiO 2 substrates for use as high-performance nanoscale transistors. These InAs layers are fully depleted, which is an important criterion for achieving high-performance field-effect transistors (FETs) with respectable 'off' currents based on small bandgap semiconductors. The transfer is achieved without the use of adhesive layers, thereby allowing the use of purely inorganic interfaces with low interface trap densities and high stability. Figure 1a shows a diagram of the fabrication process for InAs XOI substrates (see Methods for details). We used atomic force microscopy (AFM) to characterize the surface morphology and uniformity of the fabricated XOI substrates. Figure 1b and c shows representative AFM images of an array of InAs nanoribbons (,18 nm thick) on a Si/SiO 2 substrate, clearly depicting the smooth surfaces (,1 nm surface roughness) and high uniformity of the enabled structures over large areas. Uniquely, the process readily enables the heterogeneous integration of different III-V materials and structures on a single substrate through a multi-step epitaxial transfer process. To demonstrate this capability, a two-step transfer process was used to form ordered arrays of 18-and 48-nm-thick InAs nanoribbons that are perpendicularly oriented on the surface of a Si/SiO 2 substrate (Fig. 1d, e). This result demonstrates the potential capacity of the proposed XOI technology for generic heterogeneous and/or hierarchical assembly of crystalline semiconducting materials. In the future, a similar scheme may be used to enable the fabrication of both p-and n-type transistors on the same chip for complementary electronics based on the optimal III-V semiconductors.

Simulation of electronic transport in nanoscale devices plays a pivotal role in shedding light on... more Simulation of electronic transport in nanoscale devices plays a pivotal role in shedding light on underlying physics, and in guiding device-design and optimization. The length scale of the problem and the physical mechanism of device operation guide the choice of formalism. In the sub-20 nanometer regime, semi-classical approaches start breaking down, thus necessitating a quantum-mechanical treatment of the electronic transport problem. Non-equilibrium Green's function (NEGF) is a theoretical framework for investigating quantum-mechanical systems - interacting with surroundings through exchange of quasiparticles - far from equilibrium. Although hugely computation-intensive with a realistic device-representation, it provides a rigorous way to include particle-particle interactions and to model phenomena that are inherently quantum-mechanical.We build the Berkeley Quantum Transport Simulator (BQTS) - a massively parallel, generic, NEGF-based numerical simulator - to explore low-po...

70th Device Research Conference, 2012

ABSTRACT To summarize, we propose that quasi-saturation in short-channel GFET output characterist... more ABSTRACT To summarize, we propose that quasi-saturation in short-channel GFET output characteristics can be effectively engineered by doping in the drain-underlap region and show using self-consistent NEGF simulations that a 0.2% p-type doping can enhance output resistance by 13x and intrinsic gain by 4x in 20 nm gate-length GFETs.

68th Device Research Conference, 2010

ABSTRACT This paper proposes two major classes of band-to-band tunneling devices: one with an ult... more ABSTRACT This paper proposes two major classes of band-to-band tunneling devices: one with an ultra thin body double gate geometry where the tunneling is completely along the transport direction and the other, where tunneling is expected to be vertical by having a pocket (halo) in the gate-to-source overlap region. In both cases it uses InAs as the channel material. The vertical tunneling structure provides more ON current due to the dual contribution of vertical and lateral tunneling and the OFF current is determined by the same physics.

69th Device Research Conference, 2011

ABSTRACT Using ballistic NEGF-based transport simulations, we project the maximum performance ach... more ABSTRACT Using ballistic NEGF-based transport simulations, we project the maximum performance achievable with monolayer MoS2 transistors. Our simulations show that these devices can provide (i) excellent switching behavior with very high ON current, (ii) a gmof about 3 mS/μm, and (iii) immunity to short channel effects thanks to the electrostatistically efficient 2-D geometry. We have also investigated the effect of underlap, barrier height and contact resistance on the device performance. We note that while these numbers are representative of the best performance MoS2 transistors can offer, the fact that they are significantly better than those for either state-of-the-art silicon, III-V or graphene makes MoS2 devices promising for future electronic applications.

2013 IEEE International Electron Devices Meeting, 2013

The optimal performance of ultimately scaled transition metal dichalcogenide (TMD) FETs for four ... more The optimal performance of ultimately scaled transition metal dichalcogenide (TMD) FETs for four different materials and one to five layers is investigated using ballistic quantum transport calculations with material properties derived from first-principles. Large bandgaps and effective masses are shown to result in excellent switching performance at 5 nm gate lengths, thus showing potential for low-power applications. However, achievable current falls short of ITRS low operating power specifications.

Nature, 2010

Over the past several years, the inherent scaling limitations of electron devices have fueled the... more Over the past several years, the inherent scaling limitations of electron devices have fueled the exploration of high carrier mobility semiconductors as a Si replacement to further enhance the device performance 1,2,3,4,5,6,7,8. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied 7,9,10 , combining the high mobility of III-V semiconductors and the well-established, low cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored 9,11,12,13. Besides complexity, high defect densities and junction leakage currents present limitations in the

Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-chann... more Using 2-D self-consistent ballistic quantum transport simulations, we investigate the short-channel behavior of graphene field-effect transistors and its impact on the device transconductance and subsequently the intrinsic cut-off frequency (fT). Although with thin oxides, fT expectedly scales inversely with the gate length, significant band-to-band tunneling at OFF state leads to a departure from this trend in case of thick oxides. We also examine the effect of achieving better electrostatics at the cost of increased gate capacitance and illustrate that this can indeed degrade the fT. These considerations should be implicit in the optimization of graphene transistors for high-frequency applications.

Journal of Applied Physics, 2012

ABSTRACT We compare the results of self-consistent ballistic quantum transport simulation of Zene... more ABSTRACT We compare the results of self-consistent ballistic quantum transport simulation of Zener tunneling in InAs, a direct bandgap semiconductor, with corresponding semi-classical solutions using the well-known Kane’s model and the Wentzel-Kramers-Brillouin (WKB) approximation. We find a qualitative difference between solutions obtained from Kane’s formulation and rigorous quantum-mechanical formalism. However, the WKB solution, with evaluation of action integral along the tunneling paths determined from the nearest neighbor sp3s* Hamiltonian, is shown to provide qualitative agreement. We discuss the issues involved in fitting semi-classical solutions with their quantum counterpart and also present a brief comparison of our results with experimental data.

IEEE Transactions on Electron Devices, 2013

ABSTRACT With the recent upsurge in experimental efforts toward fabrication of short-channel grap... more ABSTRACT With the recent upsurge in experimental efforts toward fabrication of short-channel graphene field-effect transistors (GFETs) for analog and high-frequency RF applications-where the advantages of distinctive intrinsic properties of gapless graphene are expected to be leveraged-a critical understanding of the factors affecting both output and transfer characteristics is necessary for device optimization. Analyzing the device characteristics through ballistic electronic transport simulations within the nonequilibrium Green's function formalism, we show that a doping in the drain underlap region can significantly improve the quasi-saturation behavior in the GFET output characteristics and, hence, the output resistance and intrinsic gain. From this understanding, we provide a unified and coherent explanation for seemingly disparate phenomena-quasi-saturation and the recently reported three-terminal negative differential resistance in GFETs. We also investigate the scaling behavior of cutoff frequency and comment on some of the observed scaling trends in recent experiments.

IEEE Electron Device Letters, 2011

We propose a Heterojunction Vertical Tunneling FET and show using self-consistent ballistic quant... more We propose a Heterojunction Vertical Tunneling FET and show using self-consistent ballistic quantum transport simulations that it can provide very steep subthreshold swings and high ON current, thereby improving the scalability of Tunnel FETs for high performance. The turn-on in pocket region of the device is dictated by modulation of heterojunction barrier height. The steepness of turn-on is increased because of simultaneous onset of tunneling in the pocket and the region underneath and also due to contribution to current by vertical tunneling in the pocket. These factors can be engineered by tuning heterojunction band offsets.

Bulletin of the American Physical Society, 2011

The resurgence of interest in band-to-band tunneling has been due to its usefulness in overcoming... more The resurgence of interest in band-to-band tunneling has been due to its usefulness in overcoming the 60 mV/decade limit in turn-on characteristics of a MOSFET thereby providing path for lowering the operating power. The expression due to \textit{Kane}, for calculating transmission ...

Applied Physics Letters, 2010

Using self-consistent quantum transport simulation on realistic devices, we show that InAs band-t... more Using self-consistent quantum transport simulation on realistic devices, we show that InAs band-to-band Tunneling Field Effect Transistors (TFET) with a heavily doped pocket in the gate-source overlap region can offer larger ON current and steeper subthreshold swing as compared to conventional tunneling transistors. This is due to an additional tunneling contribution to current stemming from band overlap along the body thickness. However, a critical thickness is necessary to obtain this advantage derived from 'vertical' tunneling. In addition, in ultra small InAs TFET devices, the subthreshold swing could be severely affected by direct source-to-drain tunneling through the body.

2023 IEEE International Solid- State Circuits Conference (ISSCC), Feb 19, 2023