Ernesto Gomez Sanchez | UDC - Uniao Dinamica de Faculdades Cataratas (original) (raw)
Papers by Ernesto Gomez Sanchez
Lecture Notes in Computer Science, 2008
... 1 Politecnico di Torino Dipartimento di Automatica e Informatica - Torino, Italy {paolo.ber... more ... 1 Politecnico di Torino Dipartimento di Automatica e Informatica - Torino, Italy {paolo.bernardi, michelangelo.grosso,edgar.sanchez, matteo.sonzareorda}@polito.it 2 ... Huband, S., et al.: A Review of Multiobjective Test Problems and a Scalable Test Problem Toolkit. ...
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings., 2004
The actual operating life time for many electronic systems turned out being much longer than orig... more The actual operating life time for many electronic systems turned out being much longer than originally foreseen, leading to the use of obs olete components in critical projects. To skip microprocessor obsolescence problems, companies sho uld have bought larger stocks of components when still available, or are forced to f ind parts in secondary markets later. Alternatively, a suitable low-cost
2013 14th Latin American Test Workshop - LATW, 2013
ABSTRACT Electronic systems are increasingly used for safety-critical applications, where the eff... more ABSTRACT Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB
Springer Series in Advanced Microelectronics, 2005
This chapter describes and analyzes a methodology for gathering together test-programs for microp... more This chapter describes and analyzes a methodology for gathering together test-programs for microprocessor cores during the complete design cycle starting from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of
2007 IEEE Congress on Evolutionary Computation, 2007
Research community has not investigated as deeply as necessary the test generation problem of per... more Research community has not investigated as deeply as necessary the test generation problem of peripheral modules inside a system-on-a-chip (SoC), yet. Testing process for a peripheral core requires two distinct but highly correlated tasks: peripheral configuration and peripheral exercising. The configuration task is usually performed by an assembly program executed by the microprocessor within the SoC; whereas peripheral exercising directly concerns to the use of the device, which may be activated by both the executed program and a carefully devised set of external stimuli. When embedded in a SoC, peripheral cores introduce new issues for their testing. In this paper an automatic approach able to co- evolve assembly programs and stimuli sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The proposed method considerably reduces the required efforts to produce a suitable test set with respect to the previous approaches, broadening its applicability and increasing its usefulness.
2005 Sixth International Workshop on Microprocessor Test and Verification, 2005
... internal memory nor the IIP hardware have been included in the diagnosable mod-ules. ... The ... more ... internal memory nor the IIP hardware have been included in the diagnosable mod-ules. ... The subsequent elimination of the redun-dant programs, performed as outlined above, left us ... Resorting to the evolutionary approach aforementioned, we are able to improve the diagnostic ...
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
The ever increasing usage of microprocessor devices is sustained by a high volume production that... more The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault diagnosis is an integral part of the industrial effort towards these goals. This paper presents a new methodology that significantly improves over a previous work. The goal is construction of cost-effective programs
2005 18th Symposium on Integrated Circuits and Systems Design, 2005
Higher integration densities, smaller feature lengths, and other technology advances, as well as ... more Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs at-speed, and matches core test requirements while exploiting low-cost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that couples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 microprocessor core.
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Test of peripheral modules has not yet been deeply investigated by the research community. When e... more Test of peripheral modules has not yet been deeply investigated by the research community. When embedded in a system on a chip, peripheral cores introduce new issues for post-production testing. A peripheral core embedded in a SoC requires a test set able to properly perform two different tasks: configure the device in different operation modes and properly exercise it. In this paper an automatic approach able to generate test sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The method compares favorably with results obtained by hand.
Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No.04TH8753), 2004
Abstract This paper analyzes corewar, a very peculiar computer game popular in mid 80's wher... more Abstract This paper analyzes corewar, a very peculiar computer game popular in mid 80's where different programs fight in the memory of a virtual computer. The μGP, an evolutionary assembly-program generator, is used to evolve efficient programs, and the game is ...
2015 16th Latin-American Test Symposium (LATS), 2015
ABSTRACT
26th IEEE VLSI Test Symposium (vts 2008), 2008
This paper presents an innovative approach for the generation of functional programs to test path... more This paper presents an innovative approach for the generation of functional programs to test pathdelay faults within microprocessors. The proposed method takes advantage of both the gate-and RTlevel description of the processor. The former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times. 26th IEEE VLSI Test Symposium 1093-0167/08 $25.00
2008 Ninth International Workshop on Microprocessor Test and Verification, 2008
ABSTRACT
2009 14th IEEE European Test Symposium, 2009
Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also fo... more Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and outlines the importance of adopting a functional approach. Secondly, the paper describes a novel approach to automatically generate suitable stress patterns to be used during the
2010 11th International Workshop on Microprocessor Test and Verification, 2010
Today, electronic devices are increasingly employed in different fields, including safety- and mi... more Today, electronic devices are increasingly employed in different fields, including safety- and mission- critical applications, where the quality of the product is an essential requirement. In the automotive field, the Software- Based Self-Test is a dependability technique currently demanded by industrial standards. This paper presents an approach employed by STMicroelectronics for evaluating, or grading, the effectiveness of Software-Based Self-Test procedure
2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle... more In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions.
Lecture Notes in Computer Science, 2008
Traditional test generation methodologies for peripheral cores are performed by a skilled test en... more Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
In this paper, we propose an innovative emulation-based framework for the generation of test prog... more In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which is particularly
2007 Eighth International Workshop on Microprocessor Test and Verification, 2007
Traditional test generation methodologies for peripheral cores resort heavily to low-level descri... more Traditional test generation methodologies for peripheral cores resort heavily to low-level descriptions of the circuit, leading to long generation times. Methodologies based on high-level descriptions can only be used if a clear relationship exists between the measured high-level coverage and the gate-level fault coverage. Even in medium complexity circuits, however, a direct relationship between code coverage metrics and fault coverage is not guaranteed, while other RTlevel metrics require an effort comparable to the use of lowlevel descriptions. To overcome this problem, in the case of peripheral cores, a new approach is proposed: FSMs embedded in the system are identified and dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. Model extraction and coverage maximization are performed concurrently in a completely automated way. This new technique is exploited to drive an unsupervised methodology for generating tests for peripheral cores. Experimental analysis shows the effectiveness of the approach.
Lecture Notes in Computer Science, 2008
... 1 Politecnico di Torino Dipartimento di Automatica e Informatica - Torino, Italy {paolo.ber... more ... 1 Politecnico di Torino Dipartimento di Automatica e Informatica - Torino, Italy {paolo.bernardi, michelangelo.grosso,edgar.sanchez, matteo.sonzareorda}@polito.it 2 ... Huband, S., et al.: A Review of Multiobjective Test Problems and a Scalable Test Problem Toolkit. ...
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings., 2004
The actual operating life time for many electronic systems turned out being much longer than orig... more The actual operating life time for many electronic systems turned out being much longer than originally foreseen, leading to the use of obs olete components in critical projects. To skip microprocessor obsolescence problems, companies sho uld have bought larger stocks of components when still available, or are forced to f ind parts in secondary markets later. Alternatively, a suitable low-cost
2013 14th Latin American Test Workshop - LATW, 2013
ABSTRACT Electronic systems are increasingly used for safety-critical applications, where the eff... more ABSTRACT Electronic systems are increasingly used for safety-critical applications, where the effects of faults must be taken under control and hopefully avoided. For this purpose, test of manufactured devices is particularly important, both at the end of the production line and during the operational phase. This paper describes a method to test the logic implementing the Branch Prediction Unit in pipelined and superscalar processors when this follows the Branch Target Buffer (BTB) architecture; the proposed approach is functional, i.e., it is based on forcing the processor to execute a suitably devised test program and observing the produced results. Experimental results are provided on the DLX processor, showing that the method can achieve a high value of stuck-at fault coverage while also testing the memory in the BTB
Springer Series in Advanced Microelectronics, 2005
This chapter describes and analyzes a methodology for gathering together test-programs for microp... more This chapter describes and analyzes a methodology for gathering together test-programs for microprocessor cores during the complete design cycle starting from early design phases. The methodology is based on an almost automatic tool and could be applied to generate test-programs for stand-alone microprocessor cores as well as for these embedded in systems-on-chip. The main idea is to take advantage of
2007 IEEE Congress on Evolutionary Computation, 2007
Research community has not investigated as deeply as necessary the test generation problem of per... more Research community has not investigated as deeply as necessary the test generation problem of peripheral modules inside a system-on-a-chip (SoC), yet. Testing process for a peripheral core requires two distinct but highly correlated tasks: peripheral configuration and peripheral exercising. The configuration task is usually performed by an assembly program executed by the microprocessor within the SoC; whereas peripheral exercising directly concerns to the use of the device, which may be activated by both the executed program and a carefully devised set of external stimuli. When embedded in a SoC, peripheral cores introduce new issues for their testing. In this paper an automatic approach able to co- evolve assembly programs and stimuli sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The proposed method considerably reduces the required efforts to produce a suitable test set with respect to the previous approaches, broadening its applicability and increasing its usefulness.
2005 Sixth International Workshop on Microprocessor Test and Verification, 2005
... internal memory nor the IIP hardware have been included in the diagnosable mod-ules. ... The ... more ... internal memory nor the IIP hardware have been included in the diagnosable mod-ules. ... The subsequent elimination of the redun-dant programs, performed as outlined above, left us ... Resorting to the evolutionary approach aforementioned, we are able to improve the diagnostic ...
2007 Design, Automation & Test in Europe Conference & Exhibition, 2007
The ever increasing usage of microprocessor devices is sustained by a high volume production that... more The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault diagnosis is an integral part of the industrial effort towards these goals. This paper presents a new methodology that significantly improves over a previous work. The goal is construction of cost-effective programs
2005 18th Symposium on Integrated Circuits and Systems Design, 2005
Higher integration densities, smaller feature lengths, and other technology advances, as well as ... more Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Currently, Software-Based Self-Test (SBST) is becoming an attractive test solution since it guarantees high fault coverage figures, runs at-speed, and matches core test requirements while exploiting low-cost ATEs. However, automatically generating test programs is still an open problem. This paper presents a novel approach for test program generation, that couples evolutionary techniques with hardware acceleration. The methodology was evaluated targeting a 5-stage pipelined processor implementing a SPARCv8 microprocessor core.
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Test of peripheral modules has not yet been deeply investigated by the research community. When e... more Test of peripheral modules has not yet been deeply investigated by the research community. When embedded in a system on a chip, peripheral cores introduce new issues for post-production testing. A peripheral core embedded in a SoC requires a test set able to properly perform two different tasks: configure the device in different operation modes and properly exercise it. In this paper an automatic approach able to generate test sets for peripheral cores embedded in a SoC is described. The presented approach is based on an evolutionary algorithm that exploits high-level simulation and gathers coverage metrics information to produce the test sets. The method compares favorably with results obtained by hand.
Proceedings of the 2004 Congress on Evolutionary Computation (IEEE Cat. No.04TH8753), 2004
Abstract This paper analyzes corewar, a very peculiar computer game popular in mid 80's wher... more Abstract This paper analyzes corewar, a very peculiar computer game popular in mid 80's where different programs fight in the memory of a virtual computer. The μGP, an evolutionary assembly-program generator, is used to evolve efficient programs, and the game is ...
2015 16th Latin-American Test Symposium (LATS), 2015
ABSTRACT
26th IEEE VLSI Test Symposium (vts 2008), 2008
This paper presents an innovative approach for the generation of functional programs to test path... more This paper presents an innovative approach for the generation of functional programs to test pathdelay faults within microprocessors. The proposed method takes advantage of both the gate-and RTlevel description of the processor. The former is used to build Binary Decision Diagrams (BDDs) for deriving fault excitation conditions; the latter is exploited for the automatic generation of test programs able to excite and propagate fault effects, based on an evolutionary algorithm and fast RTL simulation. Experimental results on a simple microcontroller show that the proposed methodology is able to generate suitable test sets in reduced times. 26th IEEE VLSI Test Symposium 1093-0167/08 $25.00
2008 Ninth International Workshop on Microprocessor Test and Verification, 2008
ABSTRACT
2009 14th IEEE European Test Symposium, 2009
Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also fo... more Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and outlines the importance of adopting a functional approach. Secondly, the paper describes a novel approach to automatically generate suitable stress patterns to be used during the
2010 11th International Workshop on Microprocessor Test and Verification, 2010
Today, electronic devices are increasingly employed in different fields, including safety- and mi... more Today, electronic devices are increasingly employed in different fields, including safety- and mission- critical applications, where the quality of the product is an essential requirement. In the automotive field, the Software- Based Self-Test is a dependability technique currently demanded by industrial standards. This paper presents an approach employed by STMicroelectronics for evaluating, or grading, the effectiveness of Software-Based Self-Test procedure
2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle... more In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions.
Lecture Notes in Computer Science, 2008
Traditional test generation methodologies for peripheral cores are performed by a skilled test en... more Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodology based on an evolutionary tool which exploits high level metrics is presented. To strengthen the correlation between high-level coverage and the gate-level fault coverage, in the case of peripheral cores, the FSMs embedded in
13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
In this paper, we propose an innovative emulation-based framework for the generation of test prog... more In this paper, we propose an innovative emulation-based framework for the generation of test programs oriented to SMT microprocessor validation. The two major characteristics of the proposed framework are an effective method to gather information about the processor internal status via its emulation, and an efficient algorithm which exploits these pieces of information for a generation process which is particularly
2007 Eighth International Workshop on Microprocessor Test and Verification, 2007
Traditional test generation methodologies for peripheral cores resort heavily to low-level descri... more Traditional test generation methodologies for peripheral cores resort heavily to low-level descriptions of the circuit, leading to long generation times. Methodologies based on high-level descriptions can only be used if a clear relationship exists between the measured high-level coverage and the gate-level fault coverage. Even in medium complexity circuits, however, a direct relationship between code coverage metrics and fault coverage is not guaranteed, while other RTlevel metrics require an effort comparable to the use of lowlevel descriptions. To overcome this problem, in the case of peripheral cores, a new approach is proposed: FSMs embedded in the system are identified and dynamically extracted via simulation, while transition coverage is used as a measure of how much the system is exercised. Model extraction and coverage maximization are performed concurrently in a completely automated way. This new technique is exploited to drive an unsupervised methodology for generating tests for peripheral cores. Experimental analysis shows the effectiveness of the approach.