Dr P Vimala | Dayananda Sagar College Of Engineering (original) (raw)

Papers by Dr P Vimala

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

Journal of Electronic Materials, 2021

This research intends to develop an analytical model for a heterojunction graphene nanoribbon dou... more This research intends to develop an analytical model for a heterojunction graphene nanoribbon double-gate tunnel field-effect transistor with a stacked SiO2/HfO2 layer. Embodying indium antimony as the source material and silicon as both channel and drain material results in a heterojunction that helps in improving the proposed device's performance. A graphene nanoribbon is inserted beneath the SiO2 layer to improve the band tunneling generation rate. To study the device characteristics like ON and OFF current of the TFET, an analytical model based on the two-dimensional (2D) nonlinear Poisson equation and parabolic approximation method is developed. The proposed model is validated using a 2D technology computer-aided design numerical device simulator, and the device parameters such as surface potential, electric field, and drain current are substantiated with the analytical data.

2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC)

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

IEEE Conference Proceedings, 2020

2021 IEEE Mysore Sub Section International Conference (MysuruCon), 2021

Carrier concentration denotes the number of charge carriers per unit volume. Charge carriers invo... more Carrier concentration denotes the number of charge carriers per unit volume. Charge carriers involve equations concerning electrical conductivity as well as thermal conductivity. In this paper, the carrier concentration is calculated for intrinsic, n-type, and p-type semiconductors. The purpose of calculating carrier concentration is to find out the number of holes and electrons of different semiconductors at different temperatures and doping concentrations. This helped to analyze the properties of semiconductors. By looking at the properties one can decide the right application for the semiconductor.

2021 IEEE Mysore Sub Section International Conference (MysuruCon), 2021

Over last several decades, the role of biosensing has gained importance in the global market. The... more Over last several decades, the role of biosensing has gained importance in the global market. The nanowire biosensor characteristics is analyzed using the Biosensor Lab tool. The performance parameters such as settling time conductance modulation with respect to analytic ion concentration and target molecular density. The Diffusion-Capture model is used for simulation. The Poisson-Boltzmann and Drift-Diffusion equations are considered for analysis. The obtained results are in good agreement with theoretical concepts.

Journal of Nanotechnology and Nano-Engineering, 2021

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutti... more Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), 2020

This paper describes the novel design for a high k dielectric stacked halo surrounding gate tunne... more This paper describes the novel design for a high k dielectric stacked halo surrounding gate tunnel field effect transistor. The device is explored using realistic device parameters. The device simulation is carried on a numerical device simulating tool, Silvaco ATLAS Technology computer aided design (TCAD). The electric parameters such as surface potential and electric field are analyzed across the channel length of the device structure. The input and output characteristics are studied for halo high-k SG TFET for different bias voltages. Furthermore, the performance of the halo high-k device is compared with the surrounding gate TFETs and stacked high-k SG TFET. The comparison analysis of all the three devices shows a better performance for halo high-k SG TFETs with higher ON current and ION/IOFF{I}_{ON}/{I}_{OFF}ION/IOFF ratio resulting in promising device for circuit applications with low power and fastest switching.

Silicon, 2020

This paper investigated the design and TCAD simulation of heterojunction Tunnel Field Effect Tran... more This paper investigated the design and TCAD simulation of heterojunction Tunnel Field Effect Transistor (TFET) with dual gate material. The proposed device structure is designed with narrow bandgap semiconductor material InGaAs (0.74 eV) at source region and wider energy bandgap InP (1.34 eV) at channel and drain regions. The narrow bandgap at source/channel junction improves the tunneling generation rate and the wider bandgap at drain/channel junction reduces the ambipolar behavior. In addition to heterojunction, the dual work function at gate Metal (M 1) and Metal (M 2) and HfO 2 /SiO 2 stacked dielectric helps to improve the band-gap narrowing as well as reduced leakage current. The proposed device electrical parameters such as Surface potential, energy band diagram, electric field, transconductance and drain current has been analyzed. The simulation results show significant improvement in ON current (10 −5 A/μm) and reduced OFF current (10 −12 A/μm) in the proposed device structure. The presented result reveals that the InGaAs/InP heterojunction stacked dielectric TFET is a good candidate for low power applications.

International Journal of Computer Applications, 2016

Digital multipliers are most widely used component in applications such as convolution, Fourier t... more Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip flop is used, which results in reduced delay and increased speed than the existing system. Meanwhile proposed architecture is used to compare array multiplier, column-bypassing multiplier, row-bypassing multiplier and Vedic multiplier. The experimental result shows that the Vedic multiplier has better performance in power consumption and delay. Here in this work Vedic multiplication is done using Urdhva Tiryakbhyam Sutra (Algorithm), which results in minimum delay. Thus using Vedic multiplier ALU is designed which results in enhanced performance compared to contemporary design.

2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2021

This study traverses the comparison analysis of n channel double gate FinFET structure considerin... more This study traverses the comparison analysis of n channel double gate FinFET structure considering various semiconducting channel materials such as Silicon, Germanium and Gallium Nitride. Electrical properties namely drain current, threshold voltage and transconductance for all these devices containing above channel materials are investigated. The devices are investigated for short channel effects like drain induced barrier lowering (DIBL). All of these simulations are carried out in Nano-hub tool. Results shows better performance for germanium based double-gate device.

Nanoscience &Nanotechnology-Asia, 2018

In this article we have developed an analytical model for Double gate Metal Oxide Semiconductor F... more In this article we have developed an analytical model for Double gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) including Quantum effects. The Schrodinger-Poisson's equation is used to develop the analytical Quantum model using Variational method. A mathematical expression for charge centroid is obtained and then an inversion charge model was developed with quantum mechanical effects by means of oxide capacitance for different channel thickness and gate oxide thickness.

2020 5th International Conference on Devices, Circuits and Systems (ICDCS), 2020

In the last three decades, Scaling of complementary metal-oxide semiconductor (CMOS) technology b... more In the last three decades, Scaling of complementary metal-oxide semiconductor (CMOS) technology been gateway to continual development in the silicone basis semiconductor industry. Nevertheless, as technology scaling reaches the nanometer system, CMOS devices face many serious issues such as enhanced leakage currents, on-current difficulties, large variations in parameters, poor reliability and yield, higher manufacturing costs, and so on. The Tunnel field-effect transistor (TFET) suggested as a most propitious option compared to CMOS devices. TFET is suitable because of its steep slope possibilities and the corresponding benefits in functioning at limited supply voltage. In this paper, we explored different interface structures related to the Double Gate TFET(DG-TFET) and Triple Gate TFET(TG-TFET).

Physica E: Low-dimensional Systems and Nanostructures, 2019

This is a PDF file of an article that has undergone enhancements after acceptance, such as the ad... more This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

International journal of engineering research and technology, Jun 20, 2019

Journal of Computational Electronics, 2022

We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All... more We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All-Around Hetero Junction TFETs (GAA-HJTFETs). The hetero junction is set up by using Ge/Si material in the source/channel respectively. The modeling is accomplished by considering the space charge regions at the source-channel/drainchannel junctions and the channel region. The surface potential in the channel region is obtained by applying superposition principle, where as in source/drain it is derived by solving 2-D/1-D Poisson's equation respectively. Furthermore, the electric field and drain current are modeled from the surface potential and Kane model respectively. The results are confirmed using ATLAS TCAD simulation.

International journal of engineering research and technology, Jun 20, 2019

In recent years, graphene has shown huge promise as material that can swap silicon-based material... more In recent years, graphene has shown huge promise as material that can swap silicon-based materials in the future due to its outstanding electrical properties and other characteristics. MOSFETs have disadvantages with shorter channels causing short channel effects but Graphene has many uncommon properties. It is the strongest material ever tested, conducts heat and electricity efficiently, high mobility at room temperature, low atomic thickness, large current density, and is nearly transparent, Graphene shows a large and nonlinear diamagnetism. Graphene is an allotrope form of carbon consisting of a single layer of carbon atoms arranged in a hexagonal lattice. It is a semimetal with small overlap between the valence and the conduction bands and overall with reduced short channel effects. In this project, we propose the analytical modelling and simulation of Graphene Nanoribbon field effect transistor with armchair chirality of GNRs for semiconducting behaviour in which, we model Drain current v/s Drain voltage, Drain current v/s Gate voltage, Current density with varying channel lengths, Transconductance, Ion/Ioff ratio, Channel surface potential and Density of States using self-consistent solution of 2D Poisson equation. This project covers the studies and modelling of Graphene Nanoribbon, which includes currentvoltage graphical plots using MATLAB.

A 2-Dimensional (2D) FinFET simulation is presented in this study.The simulation studies are cond... more A 2-Dimensional (2D) FinFET simulation is presented in this study.The simulation studies are conducted based on electrical parameters such as surface potential, electric field, transfer characteristics, threshold voltage and sub threshold swing using nanohubmultiple gate field effect transistors(MUGFET) simulator. These characterization studies are performed to investigate the performance of FinFETs based on different channel width and show a better performance for lower channel width withthreshold voltage shift of 0.2 V.Further, the transfer characteristics for the device are compared with silicon dioxide and titanium oxide, as oxide material for different drain biases. Findings have shown that the device with titanium oxide as dielectric material performs better compared to silicon dioxide counterpart, where the on-statecurrent increased with decreased off current.

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

Journal of Electronic Materials, 2021

This research intends to develop an analytical model for a heterojunction graphene nanoribbon dou... more This research intends to develop an analytical model for a heterojunction graphene nanoribbon double-gate tunnel field-effect transistor with a stacked SiO2/HfO2 layer. Embodying indium antimony as the source material and silicon as both channel and drain material results in a heterojunction that helps in improving the proposed device's performance. A graphene nanoribbon is inserted beneath the SiO2 layer to improve the band tunneling generation rate. To study the device characteristics like ON and OFF current of the TFET, an analytical model based on the two-dimensional (2D) nonlinear Poisson equation and parabolic approximation method is developed. The proposed model is validated using a 2D technology computer-aided design numerical device simulator, and the device parameters such as surface potential, electric field, and drain current are substantiated with the analytical data.

2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC)

2022 6th International Conference on Devices, Circuits and Systems (ICDCS)

IEEE Conference Proceedings, 2020

2021 IEEE Mysore Sub Section International Conference (MysuruCon), 2021

Carrier concentration denotes the number of charge carriers per unit volume. Charge carriers invo... more Carrier concentration denotes the number of charge carriers per unit volume. Charge carriers involve equations concerning electrical conductivity as well as thermal conductivity. In this paper, the carrier concentration is calculated for intrinsic, n-type, and p-type semiconductors. The purpose of calculating carrier concentration is to find out the number of holes and electrons of different semiconductors at different temperatures and doping concentrations. This helped to analyze the properties of semiconductors. By looking at the properties one can decide the right application for the semiconductor.

2021 IEEE Mysore Sub Section International Conference (MysuruCon), 2021

Over last several decades, the role of biosensing has gained importance in the global market. The... more Over last several decades, the role of biosensing has gained importance in the global market. The nanowire biosensor characteristics is analyzed using the Biosensor Lab tool. The performance parameters such as settling time conductance modulation with respect to analytic ion concentration and target molecular density. The Diffusion-Capture model is used for simulation. The Poisson-Boltzmann and Drift-Diffusion equations are considered for analysis. The obtained results are in good agreement with theoretical concepts.

Journal of Nanotechnology and Nano-Engineering, 2021

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutti... more Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

2020 International Conference on Emerging Trends in Information Technology and Engineering (ic-ETITE), 2020

This paper describes the novel design for a high k dielectric stacked halo surrounding gate tunne... more This paper describes the novel design for a high k dielectric stacked halo surrounding gate tunnel field effect transistor. The device is explored using realistic device parameters. The device simulation is carried on a numerical device simulating tool, Silvaco ATLAS Technology computer aided design (TCAD). The electric parameters such as surface potential and electric field are analyzed across the channel length of the device structure. The input and output characteristics are studied for halo high-k SG TFET for different bias voltages. Furthermore, the performance of the halo high-k device is compared with the surrounding gate TFETs and stacked high-k SG TFET. The comparison analysis of all the three devices shows a better performance for halo high-k SG TFETs with higher ON current and ION/IOFF{I}_{ON}/{I}_{OFF}ION/IOFF ratio resulting in promising device for circuit applications with low power and fastest switching.

Silicon, 2020

This paper investigated the design and TCAD simulation of heterojunction Tunnel Field Effect Tran... more This paper investigated the design and TCAD simulation of heterojunction Tunnel Field Effect Transistor (TFET) with dual gate material. The proposed device structure is designed with narrow bandgap semiconductor material InGaAs (0.74 eV) at source region and wider energy bandgap InP (1.34 eV) at channel and drain regions. The narrow bandgap at source/channel junction improves the tunneling generation rate and the wider bandgap at drain/channel junction reduces the ambipolar behavior. In addition to heterojunction, the dual work function at gate Metal (M 1) and Metal (M 2) and HfO 2 /SiO 2 stacked dielectric helps to improve the band-gap narrowing as well as reduced leakage current. The proposed device electrical parameters such as Surface potential, energy band diagram, electric field, transconductance and drain current has been analyzed. The simulation results show significant improvement in ON current (10 −5 A/μm) and reduced OFF current (10 −12 A/μm) in the proposed device structure. The presented result reveals that the InGaAs/InP heterojunction stacked dielectric TFET is a good candidate for low power applications.

International Journal of Computer Applications, 2016

Digital multipliers are most widely used component in applications such as convolution, Fourier t... more Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip flop is used, which results in reduced delay and increased speed than the existing system. Meanwhile proposed architecture is used to compare array multiplier, column-bypassing multiplier, row-bypassing multiplier and Vedic multiplier. The experimental result shows that the Vedic multiplier has better performance in power consumption and delay. Here in this work Vedic multiplication is done using Urdhva Tiryakbhyam Sutra (Algorithm), which results in minimum delay. Thus using Vedic multiplier ALU is designed which results in enhanced performance compared to contemporary design.

2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2021

This study traverses the comparison analysis of n channel double gate FinFET structure considerin... more This study traverses the comparison analysis of n channel double gate FinFET structure considering various semiconducting channel materials such as Silicon, Germanium and Gallium Nitride. Electrical properties namely drain current, threshold voltage and transconductance for all these devices containing above channel materials are investigated. The devices are investigated for short channel effects like drain induced barrier lowering (DIBL). All of these simulations are carried out in Nano-hub tool. Results shows better performance for germanium based double-gate device.

Nanoscience &Nanotechnology-Asia, 2018

In this article we have developed an analytical model for Double gate Metal Oxide Semiconductor F... more In this article we have developed an analytical model for Double gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET) including Quantum effects. The Schrodinger-Poisson's equation is used to develop the analytical Quantum model using Variational method. A mathematical expression for charge centroid is obtained and then an inversion charge model was developed with quantum mechanical effects by means of oxide capacitance for different channel thickness and gate oxide thickness.

2020 5th International Conference on Devices, Circuits and Systems (ICDCS), 2020

In the last three decades, Scaling of complementary metal-oxide semiconductor (CMOS) technology b... more In the last three decades, Scaling of complementary metal-oxide semiconductor (CMOS) technology been gateway to continual development in the silicone basis semiconductor industry. Nevertheless, as technology scaling reaches the nanometer system, CMOS devices face many serious issues such as enhanced leakage currents, on-current difficulties, large variations in parameters, poor reliability and yield, higher manufacturing costs, and so on. The Tunnel field-effect transistor (TFET) suggested as a most propitious option compared to CMOS devices. TFET is suitable because of its steep slope possibilities and the corresponding benefits in functioning at limited supply voltage. In this paper, we explored different interface structures related to the Double Gate TFET(DG-TFET) and Triple Gate TFET(TG-TFET).

Physica E: Low-dimensional Systems and Nanostructures, 2019

This is a PDF file of an article that has undergone enhancements after acceptance, such as the ad... more This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

International journal of engineering research and technology, Jun 20, 2019

Journal of Computational Electronics, 2022

We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All... more We use superposition method to model the electrostatic characteristics of high-k stacked Gate-All-Around Hetero Junction TFETs (GAA-HJTFETs). The hetero junction is set up by using Ge/Si material in the source/channel respectively. The modeling is accomplished by considering the space charge regions at the source-channel/drainchannel junctions and the channel region. The surface potential in the channel region is obtained by applying superposition principle, where as in source/drain it is derived by solving 2-D/1-D Poisson's equation respectively. Furthermore, the electric field and drain current are modeled from the surface potential and Kane model respectively. The results are confirmed using ATLAS TCAD simulation.

International journal of engineering research and technology, Jun 20, 2019

In recent years, graphene has shown huge promise as material that can swap silicon-based material... more In recent years, graphene has shown huge promise as material that can swap silicon-based materials in the future due to its outstanding electrical properties and other characteristics. MOSFETs have disadvantages with shorter channels causing short channel effects but Graphene has many uncommon properties. It is the strongest material ever tested, conducts heat and electricity efficiently, high mobility at room temperature, low atomic thickness, large current density, and is nearly transparent, Graphene shows a large and nonlinear diamagnetism. Graphene is an allotrope form of carbon consisting of a single layer of carbon atoms arranged in a hexagonal lattice. It is a semimetal with small overlap between the valence and the conduction bands and overall with reduced short channel effects. In this project, we propose the analytical modelling and simulation of Graphene Nanoribbon field effect transistor with armchair chirality of GNRs for semiconducting behaviour in which, we model Drain current v/s Drain voltage, Drain current v/s Gate voltage, Current density with varying channel lengths, Transconductance, Ion/Ioff ratio, Channel surface potential and Density of States using self-consistent solution of 2D Poisson equation. This project covers the studies and modelling of Graphene Nanoribbon, which includes currentvoltage graphical plots using MATLAB.

A 2-Dimensional (2D) FinFET simulation is presented in this study.The simulation studies are cond... more A 2-Dimensional (2D) FinFET simulation is presented in this study.The simulation studies are conducted based on electrical parameters such as surface potential, electric field, transfer characteristics, threshold voltage and sub threshold swing using nanohubmultiple gate field effect transistors(MUGFET) simulator. These characterization studies are performed to investigate the performance of FinFETs based on different channel width and show a better performance for lower channel width withthreshold voltage shift of 0.2 V.Further, the transfer characteristics for the device are compared with silicon dioxide and titanium oxide, as oxide material for different drain biases. Findings have shown that the device with titanium oxide as dielectric material performs better compared to silicon dioxide counterpart, where the on-statecurrent increased with decreased off current.