International Conference on Computer Design 2006 (original) (raw)

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CDES 2006: Las Vegas, Nevada, USA

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  • Algorithms and Hardware Design + VLSI
  • Circuit Design and Related Issues
  • Power and Energy
  • State of the Art Approach for Computer Design
  • Memory and Associated Algorithms
  • High-Performance Systems and Design Issues
  • CNAN'06 - Bio-Inspired and Nano-Scale Integrated Computing
  • CNAN'06 - Nanotechnology
  • Late Papers

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    Hamid R. Arabnia, Mary Mehrnoosh Eshaghian-Wilner:
    Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006. CSREA Press 2006, ISBN 1-60132-009-4

Algorithms and Hardware Design + VLSI

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    Martin Uhl, Werner Held:
    On the Management of Object Interrelationships. CDES 2006: 3-9
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    Sirzat Kahramanli, Suleyman Tosun:
    A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization. CDES 2006: 10-16
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    Mohamed M. Zahran, Manoj Franklin:
    RHT: A Context-Based Return Address Predictor. CDES 2006: 17-23
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    Jinming Ge:
    Round-Robin Arbiter Design. CDES 2006: 24-28
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    Suleyman Tosun, Mahmut T. Kandemir, Hakduran Koc:
    Using Task Recomputation During Application Mapping in Parallel Embedded Architectures. CDES 2006: 29-35
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    Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia:
    A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. CDES 2006: 36-38
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    Jaafar Alghazo:
    Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAs. CDES 2006: 39-45
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    Vazgen Karapetyan:
    An Algorithm for Yield Improvement via Local Positioning and Resizing. CDES 2006: 46-49
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    Abby A. Ilumoka, Yeonbum Park:
    ANN-Based Spiral Inductor Parameter Extraction and Layout Re-Design. CDES 2006: 50-56

Circuit Design and Related Issues

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    Waleed K. Al-Assadi, Vipin Sharma, Pavankumar Chandrasekhar:
    Crosstalk at the Dynamic Node of Domino CMOS Circuits. CDES 2006: 57-63
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    Himanshu Thapliyal, Hamid R. Arabnia:
    Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation. CDES 2006: 64-69
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    Himanshu Thapliyal, Hamid R. Arabnia:
    A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications. CDES 2006: 70-76

Power and Energy

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    Ahmed Sayed, Hussain Al-Asaad:
    Survey and Evaluation of Low-Power Flip-Flops. CDES 2006: 77-83
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    Nagm Mohamed, Nazeih Botros, Wei Zhang:
    The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. CDES 2006: 84-90
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    Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung:
    Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. CDES 2006: 91-96
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    Moises Zarate, Oscar Camacho Nieto, Luis A. Villa Vargas, Osvaldo Espinosa:
    Zero Detect-Based Low Power Registers File Access. CDES 2006: 97-100

State of the Art Approach for Computer Design

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    Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury:
    Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES 2006: 101-106
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    Kamala Krithivasan, Prahladh Harsha, Muralidhar Talupur:
    Communicating Distributed H systems with Simple Splicing Rules. CDES 2006: 107-111
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    Arun N. Chandorkar, Gurvinder Singh:
    Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter. CDES 2006: 112-117
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    Saad Osman Abdalla Subair, Safaai Deris:
    Protein Secondary Structure Prediction Accuracy versus Reduction Methods. CDES 2006: 118-124
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    Kamala Kritihivasan, Anshu Bhatia, T. S. Chandra:
    Simulation of a Turing Machine using EndoII Splicing Rules. CDES 2006: 125-129
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    Himanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia:
    Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations. CDES 2006: 130-134

Memory and Associated Algorithms

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    Elias G. Khalaf, Ralph Tucci:
    Semi-Contiguous Memory Allocation for Efficient Sequential-Access. CDES 2006: 135-140
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    Ayman Elnaggar, Mokhtar Aboelaze:
    Reducing Memory References for FFT Calculation. CDES 2006: 141-145
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    Hui-Chin Yang, Chung-Ping Chung:
    Autonomous Instruction Memory Equipped with Dynamic Branch Handling Capability. CDES 2006: 146-152
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    Anasua Bhowmik, Mohamed M. Zahran:
    Bandwidth-Friendly Cache Hierarchy. CDES 2006: 153-159
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    Gabriel Dragffy, Mohammad Samie, Ebrahim Farjah:
    Bio-Inspired Celluar Systems With Cyclic Metamorphic Memory. CDES 2006: 160-168

High-Performance Systems and Design Issues

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    Yajuvendra Nagaonkar, Mark L. Manwaring:
    An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation. CDES 2006: 169-174
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    Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang:
    New DSP Benchmark based on Selectable Mode Vocoder (SMV). CDES 2006: 175-181
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    Tsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen, Jia-Shian Wu:
    Improving the System Performance by a Dynamic File Prediction Model. CDES 2006: 182-188
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    Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
    A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
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    Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin:
    Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors. CDES 2006: 196-202
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    Xiaobo Li, Ke Luo, Xiangdong Cui, Lalin Jiang, Xiaoqiang Ni, Chiyuan Ma, Jingfei Jiang, Huiping Zhou, Zhou Zhou:
    A New Processor Architecture with a New Program Driving Method. CDES 2006: 203-206
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    Sandeep S. Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler:
    A Configuration Concept for a Massively Parallel FPGA Architecture. CDES 2006: 207-212

CNAN'06 - Bio-Inspired and Nano-Scale Integrated Computing

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    Dmitri B. Strukov, Konstantin K. Likharev:
    CMOL FPGA circuits. CDES 2006: 213-219
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    Mary Mehrnoosh Eshaghian-Wilner, Alexander Khitun, Shiva Navab, Kang L. Wang:
    Hierarchical Multi-Scale Architectures with Spin Waves. CDES 2006: 220-226
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    Alice C. Parker, Aaron K. Friesz, Afshaneh Pakdaman:
    Towards a Nanoscale Artificial Cortex. CDES 2006: 227-241
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    Mary Mehrnoosh Eshaghian-Wilner, Ling Lau, Shiva Navab, David Shen:
    Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable Meshes. CDES 2006: 242-250

CNAN'06 - Nanotechnology

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    Thomas P. Way:
    Compilation for Future Nanocomputer Architectures. CDES 2006: 251-257
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    Bryan W. Wagner, Thomas P. Way:
    MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer Architectures. CDES 2006: 258-264
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    Yang Wang, G. Malcolm Stocks, Aurelian Rusanu, Donald M. C. Nicholson, Markus Eisenbach, J. S. Faulkner:
    Teraflop Computing for Nanoscience. CDES 2006: 265-271
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    Esteban García Tamayo, Juan Ospina:
    A Computer Algebra Algorithm for the Symbolic Solution of a Problem involving the diffusion of adatoms on a Circular Wafer when sculpting a Nanopore with an Ion Beam. CDES 2006: 272-280

Late Papers

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    Narendra Ahuja, Garimella Rama Murthy:
    Novel Complex Vauled Neural Networks. CDES 2006: 281-286
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    Tulin Mangir:
    Integrity and Integration Issues for Nano-Tube Based Interconnect Systems. CDES 2006: 287-

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