dblp: VLSI Design 2009 (original) (raw)

default search action

• combined dblp search
• author search
• venue search
• publication search

Authors:

• no matches
• 

Venues:

• no matches
• 

Publications:

• no matches
• 

22nd VLSI Design 2009: New Delhi, India

• 

• 

• 

• 

• 
  jump to

  • Invited Talks/Special Sessions
  • Tutorials
  • Fault Diagnosis
  • Network on Chip
  • Test Generation
  • Invited Talk
  • Secure VLSI Design
  • Routing, Power Optimization
  • Reliability and Design Space Exploration
  • Timing Analysis and Optimization
  • VLSI Education

• 

• > Home > Conferences and Workshops > VLSI Design

SPARQL queries

Refine list

refinements active!

zoomed in on ?? of ?? records

view refined list in

export refined list as

• 
  VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009. IEEE Computer Society 2009, ISBN 978-0-7695-3506-7

Invited Talks/Special Sessions

• 
  Grant Martin:
  A Decade of Platform-Based Design: A look backwards, a look forwards. 3
• 
  Willy M. C. Sansen:
  Analog IC Design in Nanometer CMOS Technologies. 4
• 
  Sumit DasGupta:
  Common Power Format: A User-driven Ecosystem For Proven Low Power Design Flows. 5
• 
  Stephen Bailey:
  The Future of Low Power Design is Here: IEEE P1801, aka, UPF 2.0. 6
• 
  Gary Delp:
  Making Sense Out of the Potential Babble of Low Power Standards. 7
• 
  Robert C. Aitken:
  DFX and Productivity. 8
• 
  Vivek Singh:
  Computational Lithography - Moore Bang for your Buck. 9

Made For India Forum

• 
  Rajiv Kapur:
  Made for India Forum. 13

Panels

• 
  Ghasi Agarwal, Prakash Bare:
  Why is Design Automation and Reuse of Analog Designs Increasingly Trailing the Digital World? 17
• 
  Raman Santhanakrishnan, Yatin Trivedi:
  EDA Made-in-India: Fact or Fiction? 18
• 
  Solutions for a small car - Made for India and Made in India. 19
• 
  Accelerating Embedded System Design. 20

Tutorials

• 
  Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
  Defect Aware to Power Conscious Tests - The New DFT Landscape. 23-25
• 
  Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín:
  Techniques for the Design of Low Voltage Power Efficient Analog and Mixed Signal Circuits. 26-27
• 
  Anmol Mathur, Qi Wang:
  Power Reduction Techniques and Flows at RTL and System Level. 28-29
• 
  Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel:
  Security and Dependability of Embedded Systems: A Computer Architects' Perspective. 30-32
• 
  Goutam Debnath, Paul J. Thadikaran:
  Design for Manufacturability and Reliability in Nano Era. 33-34
• 
  Nagendra Krishnapura, Shanthi Pavan:
  Negative Feedback System and Circuit Design. 35-36
• 
  Ajit Pal, Santanu Chattopadhyay:
  Synthesis & Testing for Low Power. 37-38
• 
  Samarjit Chakraborty, Ye Wang:
  Power Management for Mobile Multimedia: From Audio to Video & Games. 39-40
• 
  Saurabh K. Tiwary, Amith Singhee, Vikas Chandra:
  Robust Circuit Design: Challenges and Solutions. 41-42

Low Power Design for Wireless Communication

SoC Verification

• 
  Prabhat Mishra, Mingsong Chen:
  Efficient Techniques for Directed Test Generation Using Incremental Satisfiability. 65-70
• 
  Aritra Hazra, Priyankar Ghosh, Pallab Dasgupta, Partha Pratim Chakrabarti:
  Inline Assertions - Embedding Formal Properties in a Test Bench. 71-76
• 
  Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham:
  Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. 77-82

Fault Diagnosis

• 
  Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume:
  A Novel Approach for Improving the Quality of Open Fault Diagnosis. 85-90
• 
  Hiroyuki Yotsuyanagi, Masaki Hashizume, Toshiyuki Tsutsumi, Koji Yamazaki, Takashi Aikyo, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu:
  Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. 91-96
• 
  Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi:
  Efficient Grouping of Fail Chips for Volume Yield Diagnostics. 97-102

Analog and Mixed Signal I

• 
  S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya:
  100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS. 105-110
• 
  Theja Tulabandhula, Yujendra Mitikiri:
  A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS. 111-116
• 
  Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas:
  Design of a Low Power, Variable-Resolution Flash ADC. 117-122

Floorplanning and Analog Layout

• 
  Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay:
  Floorplanning for Partial Reconfiguration in FPGAs. 125-130
• 
  Almitra Pradhan, Ranga Vemuri:
  Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. 131-136
• 
  Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
  Efficient Analog/RF Layout Closure with Compaction Based Legalization. 137-142

Network on Chip

• 
  Tameesh Suri, Aneesh Aggarwal:
  Improving Scalability and Per-Core Performance in Multi-Cores through Resource Sharing and Reconfiguration. 145-150
• 
  Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
  Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. 151-156
• 
  Amir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari:
  Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. 157-162
• 
  Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur:
  Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. 163-168

Low Power Device Technology

• 
  Sanjay Kumar Wadhwa:
  A Low Voltage CMOS Proportional-to-Absolute Temperature Current Reference. 171-174
• 
  Bardia Bozorgzadeh, Ali Afzali-Kusha:
  Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies. 175-180
• 
  Tamal Das, Pradip Mandal:
  Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple. 181-186

System Synthesis

• 
  Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler:
  Reversible Logic Synthesis with Output Permutation. 189-194
• 
  Suresh Raman, Mike Lubyanitsky:
  Cone Resynthesis ECO Methodology for Multi-Million Gate Designs. 195-199
• 
  Sandro Penolazzi, Ahmed Hemani, Luca Bolognino:
  A General Approach to High-Level Energy and Performance Estimation in SoCs. 200-205
• 
  V. Siva Sankar, H. Narayanan, Sachin B. Patkar:
  Exploiting Hybrid Analysis in Solving Electrical Networks. 206-211

Test Generation

• 
  Irith Pomeranz, Sudhakar M. Reddy:
  The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. 215-220
• 
  Boxue Yin, Dong Xiang, Zhen Chen:
  New Techniques for Accelerating Small Delay ATPG and Generating Compact Test Sets. 221-226
• 
  Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
  TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. 227-232
• 
  Kunal P. Ganeshpure, Sandip Kundu:
  An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. 233-238

Advanced Device Modeling

• 
  Ratul Kumar Baruah, Santanu Mahapatra:
  Concept of "Crossover Point" and its Application on Threshold Voltage Definition for Undoped-Body Transistors. 241-246
• 
  Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya:
  Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design. 247-252
• 
  Abhisek Dixit, Anirban Bandhyopadhyay, Nadine Collaert, Kristin De Meyer, Malgorzata Jurczak:
  Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack. 253-258

Application-Specific Architectures and Reconfigurable Computing

• 
  Spyros Apostolacos, George Lykakis, Apostolos Meliones, Vassilis Vlagoulis, Emmanuel Touloupis, George E. Konstantoulakis:
  Design, Implementation and Validation of an Open Source IP-PBX/VoIP Gateway SoC. 261-266
• 
  Manish Kumar Jaiswal, Nitin Chandrachoodan:
  Efficient Implementation of Floating-Point Reciprocator on FPGA. 267-271

Invited Talk

• 
  Mona Mathur:
  ReConfigurable Technologies. 272

Embedded Systems I

• 
  Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
  High-Speed On-Chip Event Counters for Embedded Systems. 275-280
• 
  Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
  A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. 281-286
• 
  Sang-Kyo Han, SeongHoon Woo, Mun-Ho Jeong, Bum-Jae You:
  Improved-Quality Real-Time Stereo Vision Processor. 287-292

SRAM and Random Number Generation

• 
  Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto:
  A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. 295-300
• 
  Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy:
  A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. 301-306
• 
  Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
  Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. 307-312

Secure VLSI Design

• 
  Debasri Saha, Susmita Sur-Kolay:
  Encoding of Floorplans through Deterministic Perturbation. 315-320
• 
  Kuan Jen Lin, Yi Tang Chiu, Shan Chien Fang:
  Design Optimization and Automation for Secure Cryptographic Circuits. 321-326
• 
  Mainak Banga, Michael S. Hsiao:
  A Novel Sustained Vector Technique for the Detection of Hardware Trojans. 327-332

Embedded Systems II

• 
  Xiaoke Qin, Prabhat Mishra:
  Efficient Placement of Compressed Code for Parallel Decompression. 335-340
• 
  Vinay B. Y. Kumar, Siddharth Joshi, Sachin B. Patkar, H. Narayanan:
  FPGA Based High Performance Double-Precision Matrix Multiplication. 341-346
• 
  J. Manikandan, B. Venkataramani, V. Avanthi:
  FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. 347-352
• 
  Prashant Bhargava, Mohit Arora:
  A "Stitch" in Time: Accurate Timekeeping with On-Chip Compensation. 353-358

Analog and Mixed Signal II

• 
  Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
  Systematic Methodology for High-Level Performance Modeling of Analog Systems. 361-366
• 
  Leburu Manojkumar, Arun Mohan, Nagendra Krishnapura:
  A Comparison of Approaches to Carrier Generation for Zigbee Transceivers. 367-372
• 
  Vijay Khawshe, Kapil Vyas, Renu Rangnekar, Prateek Goyal, Vijay Krishna, Kashinath Prabhu, Pravin Kumar Venkatesan, Leneesh Raghavan, Rajkumar Palwai, M. Thrivikraman, Kunal Desai, Abhijit Abhyankar:
  A 2.4Gbps-4.8Gbps XDR-DRAM I/O (XIO) Link. 373-378

Routing, Power Optimization

• 
  Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
  Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. 381-386
• 
  Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta:
  A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. 387-392
• 
  Kaleem Fatima, Rameshwar Rao:
  A New Hardware Routing Accelerator for Multi-Terminal Nets. 393-398
• 
  Shashank Prasad, Anuj Kumar:
  Simultaneous Routing and Feedthrough Algorithm to Decongest Top Channel. 399-403

Low Power Design

Analog and Mixed Signal III

• 
  Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil:
  Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization. 427-432
• 
  Shubhankar Basu, Balaji Kommineni, Ranga Vemuri:
  Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. 433-438
• 
  Ramen Dutta, T. K. Bhattacharyya:
  A Low Power Architecture to Extend the Tuning Range of a Quadrature Clock. 439-444
• 
  Angan Das, Ranga Vemuri:
  Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. 445-450

Reliability and Design Space Exploration

• 
  Koustav Bhattacharya, Nagarajan Ranganathan:
  RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. 453-458
• 
  Fan Wang, Vishwani D. Agrawal:
  Soft Error Rates with Inertial and Logical Masking. 459-464
• 
  Unmesh D. Bordoloi, Samarjit Chakraborty:
  Accelerating System-Level Design Tasks Using Commodity Graphics Hardware: A Case Study. 465-470

BIST, Error Modeling

• 
  V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani:
  Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. 473-478
• 
  Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar:
  WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. 479-484
• 
  Karthikeyan Lingasubramanian, Sanjukta Bhanja:
  An Error Model to Study the Behavior of Transient Errors in Sequential Circuits. 485-490

Advanced Nanodevice Modeling

• 
  Surya Shankar Dan, Santanu Mahapatra:
  Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin Modeling. 493-498
• 
  Sudeep Pasricha, Nikil D. Dutt, Fadi J. Kurdahi:
  Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications. 499-504
• 
  K. C. Narasimhamurthy, Roy P. Paily:
  Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. 505-510
• 
  Himanshu Thapliyal, Nagarajan Ranganathan:
  Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. 511-516

Timing Analysis and Optimization

• 
  Ramamurthy Vishweshwara, Ramakrishnan Venkatraman, H. Udayakumar, N. V. Arvind:
  An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis. 519-524
• 
  R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao:
  Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. 525-530

Invited Talk

• 
  Saraju P. Mohanty:
  Unified Challenges in Nano-CMOS High-Level Synthesis. 531

Processor Design and Scheduling

• 
  Sandeep Sirsi, Aneesh Aggarwal:
  Exploring the Limits of Port Reduction in Centralized Register Files. 535-540
• 
  Ramkumar Jayaseelan, Tulika Mitra:
  Temperature Aware Scheduling for Embedded Processors. 541-546
• 
  Weixun Wang, Prabhat Mishra, Ann Gordon-Ross:
  SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems. 547-552
• 
  Sourav Roy:
  H-NMRU: A Low Area, High Performance Cache Replacement Policy for Embedded Processors. 553-558

VLSI Education

• 
  Bernard Courtois, Kholdoun Torki, Sophie Dumont, Sylvaine Eyraud, Jean-François Paillotin, Gregory di Pendina:
  Infrastructures for Education, Research and Industry in Microelectronics A Look Worldwide and a Look at India. 561-566

Invited Paper-Phase Locked Loops

• 
  Prakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal:
  Specification Driven Design of Phase Locked Loops. 569-578

Invited Paper-Design for Variations

• 
  Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy:
  Coping with Variations through System-Level Design. 581-586

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.

Unpaywalled article links

Add open access links from to the list of external document links (if available).

load links from unpaywall.org

Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.

Archived links via Wayback Machine

For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).

load content from archive.org

Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.

Reference lists

Add a list of references from , , and to record detail pages.

load references from crossref.org and opencitations.net

Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.

Citation data

Add a list of citing articles from and to record detail pages.

load citations from opencitations.net

Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.

OpenAlex data

Load additional information about publications from .

load data from openalex.org

Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.

dblp was originally created in 1993 at:

since 2018, dblp has been operated and maintained by: