dblp: G. Seetharaman (disambiguation) (original) (raw)

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Gopalakrishnan Seetharaman – Seetharaman Gopalakrishnan

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This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2020 – today

• 2026
• 
  [j12]
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    Jayshree, Gopalakrishnan Seetharaman, Jitendra Kumar:
    Adaptive congestion-aware high performance scalable 2-D and 3-D topologies for network-on-chip based interconnect for quantum computing. Integr. 107: 102597 (2026)
• 2025
• 
  [j11]
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    Kavitha Veerappan, G. Seetharaman:
    Effective energy detection using machine learning techniques for cooperative sensing in cognitive radio networks. Multim. Tools Appl. 84(26): 31047-31068 (2025)
• 2023
• 
  [j10]
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    Poornima Narayanasamy, Seetharaman Gopalakrishnan:
    Novel fault tolerance topology using corvus seek algorithm for application specific NoC. Integr. 89: 146-154 (2023)
• 2022
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  [j9]
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    Kulandaivel Balakrishnan, Ramasamy Dhanalakshmi, Gopalakrishnan Seetharaman:
    S-shaped and V-shaped binary African vulture optimization algorithm for feature selection. Expert Syst. J. Knowl. Eng. 39(10) (2022)
• 2021
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  [j8]
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    Poornima Narayanasamy, Seetharaman Gopalakrishnan, Santhi Muthurathinam:
    Custom NoC topology generation using Discrete Antlion Trapping Mechanism. Integr. 76: 76-86 (2021)

2010 – 2019

• 2018
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  [j7]
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    Godwin Enemali, Adewale Adetomi, Gopalakrishnan Seetharaman, Tughrul Arslan:
    A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(5): 612-616 (2018)
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  [c8]
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    Jayshree, G. Seetharaman:
    Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay. AHS 2018: 204-209
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  [c7]
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    Poornima Narayanasamy, Santhi Muthurathinam, Seetharaman Gopalakrishnan, Tughrul Arslan, Sithu D. Sudarsan:
    R3ToS based Partially Reconfigurable Data Flow Pipelined Network on chip. AHS 2018: 210-213
• 2017
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  [c6]
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    N. Poomima, Gopalakrishnan Seetharaman, Tughrul Arslan, T. N. Prabakar, Saurav Sarkar, M. Santhi:
    Design of reconfigurable and reliable application specific network on chip for R3TOS. AHS 2017: 145-152
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  [c5]
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    N. Poornima, Seetharaman Gopalakrishnan, Tughrul Arslan, T. N. Prabakar, M. Santhi:
    Design of R3TOS based reliable low power network on chip. EST 2017: 196-203
• 2014
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  [j6]
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    M. Maheswari, G. Seetharaman:
    Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link. J. Electron. Test. 30(4): 387-400 (2014)
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  [j5]
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    M. Maheswari, G. Seetharaman:
    Design of a novel error correction coding with crosstalk avoidance for reliable on-chip interconnection link. Int. J. Comput. Appl. Technol. 49(1): 80-88 (2014)
• 2013
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  [j4]
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    M. Maheswari, G. Seetharaman:
    Multi bit random and burst error correction code with crosstalk avoidance for reliable on chip interconnection links. Microprocess. Microsystems 37(4-5): 420-429 (2013)
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  [c4]
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    Parvatham Vijay, Seetharaman Gopalakrishnan:
    Implementation of One Level 2D DWT Using Multiplier Less Modified Flipping Architecture. Asia International Conference on Modelling and Simulation 2013: 137-142
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  [c3]
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    Venkatasubramanian Adhinarayanan, Rengaprabhu Paramasivam, Seetharaman Gopalakrishnan:
    ASIC Implementation of One Level 2D-DWT Using Wave-Pipelining. Asia International Conference on Modelling and Simulation 2013: 172-175

2000 – 2009

• 2009
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  [j3]
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    G. Seetharaman, B. Venkataramani:
    Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ACM Trans. Reconfigurable Technol. Syst. 2(2): 11:1-11:19 (2009)
• 
  [c2]
  V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani:
  Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. VLSI Design 2009: 473-478
• 2008
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  [j2]
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    G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan:
    Automation techniques for implementation of hybrid wave-pipelined 2D DWT. J. Real Time Image Process. 3(3): 217-229 (2008)
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  [j1]
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    Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan:
    VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. VLSI Design 2008: 512746:1-512746:8 (2008)
• 2007
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  [c1]
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    Gopalakrishnan Seetharaman, Balasubramanian Venkataramani:
    SOC implementation of wave-pipelined circuits. FPT 2007: 9-16

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