Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation--part I: CNFET transistor optimization (original) (raw)

Chen, R. et al. (2022) Carbon nanotube SRAM in 5-nm technology node design, optimization, and performance evaluation--part I: CNFET transistor optimization.IEEE Transactions on Very Large Scale Integration Systems, 30(4), pp. 432-439. (doi: 10.1109/TVLSI.2022.3146125)

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Abstract

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a carbon nanotube (CNT) SRAM array composed of the schematically optimized CNFET SRAM and CNT interconnects. We consider the interconnects inside the CNFET SRAM cell composed of metallic single-wall CNT (M-SWCNT) bundles to represent the metal layers 0 and 1 (M0 and M1). We investigate the layout structure of CNFET SRAM cell considering CNFET devices, M-SWCNT interconnects, and metal electrode Palladium with CNT (Pd-CNT) contacts. Two versions of cell layout designs are explored and compared in terms of performance, stability, and power efficiency. Furthermore, we implement a 16 Kbit SRAM array composed of the proposed CNFET SRAM cells, multiwall CNT (MWCNTs) inter-cell interconnects and Pd-CNT contacts. Such an array shows significant advantages, with the read and write overall energy-delay product (EDP), static power consumption, and core area of 0.28x, 0.52x, and 0.76x respectively to 7-nm FinFET-SRAM array with copper interconnects, whereas the read and write static noise margins are 6% and 12% respectively larger than the FinFET counterpart.

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Funder and Project Information

CONNECT

Asen Asenov

688612

ENG - Electronics & Nanoscale Engineering

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