Jyoti Kandpal | G.B.P.U.A.&T., PANTNAGAR, UTTARAKHAND, INDIA (original) (raw)
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International Journal of Engineering Research and Applications (IJERA)
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Papers by Jyoti Kandpal
INTERNATIONAL JOURNAL OF INNOVATIONS IN MANAGEMENT, SCIENCE AND ENGINEERING, 2020
Advantage of error detection and correction techniques along with information theory is that it e... more Advantage of error detection and correction techniques along with information theory is that it enables reliable delivery of digitized data over communication channels that might be unreliable. Multiple communication channels while operating have to handle the channel noise resulting in errors occurring during transmission from transmitter to a receiver located at some distance. In this paper, a sophisticated error control coding i.e. Reed Solomon Coding technique has been implemented using VHDL and implementation is done on Virtex XC6VLX50 FPGA. The simulation result shows successful design of transmitter and receiver section. We also make use of the clock gating technique for reducing the power consumption of the design
Nowadays most of the communication is done by using digital communication systems. Therefore a Da... more Nowadays most of the communication is done by using digital communication systems. Therefore a Data protection plays an important role in the communication engineering. So, there arises a need to secure data from hackers. Hence the concept of Cryptography came in light. Earlier Data Encryption Standard (DES) was in trend but in that there were several shortcomings like the size of digital key was small and in this way it was sensible to external attacks moreover it was not able to present features that would held good for high level security system. New algorithm Advanced Encryption Standard (AES) removes loopholes.In AES Encryption algorithm Sub Bytes transformation utilizes S-Box. The subordinate Bytes replacement could be a nonlinear Byte replacement that utilizes substitution table (i.e. S-Box) takes the multiplicative inverse (GF (2 8)) and implies an affine transform to do the Sub Bytes transformation. In this research work I explored substitution table, multiplicative inverse and affine transform mathematics in Galois field; besides I recommended an encryption table to further encode the yield information.
2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC), 2019
In this paper, a high speed and low power XOR-XNOR circuit in hybrid logic style in 90 nm CMOS te... more In this paper, a high speed and low power XOR-XNOR circuit in hybrid logic style in 90 nm CMOS technology is presented. The proposed XOR-XNOR circuit is symmetrical and has only single pass transistor in all delay paths. The designed circuit provides simultaneous generation of XOR-XNOR logic, balanced output and exhibits full voltage swing in all internal and external nodes. Due to full swing in delay path, the circuit has high portability, high noise robustness, and good driving capabilities. The simulation results show 8%, 5%, and 13.2% improvement in delay, power consumption and Power Delay Product (PDP), respectively. The circuit has used only 10 transistors.
INTERNATIONAL JOURNAL OF INNOVATIONS IN MANAGEMENT, SCIENCE AND ENGINEERING, 2020
Advantage of error detection and correction techniques along with information theory is that it e... more Advantage of error detection and correction techniques along with information theory is that it enables reliable delivery of digitized data over communication channels that might be unreliable. Multiple communication channels while operating have to handle the channel noise resulting in errors occurring during transmission from transmitter to a receiver located at some distance. In this paper, a sophisticated error control coding i.e. Reed Solomon Coding technique has been implemented using VHDL and implementation is done on Virtex XC6VLX50 FPGA. The simulation result shows successful design of transmitter and receiver section. We also make use of the clock gating technique for reducing the power consumption of the design
Nowadays most of the communication is done by using digital communication systems. Therefore a Da... more Nowadays most of the communication is done by using digital communication systems. Therefore a Data protection plays an important role in the communication engineering. So, there arises a need to secure data from hackers. Hence the concept of Cryptography came in light. Earlier Data Encryption Standard (DES) was in trend but in that there were several shortcomings like the size of digital key was small and in this way it was sensible to external attacks moreover it was not able to present features that would held good for high level security system. New algorithm Advanced Encryption Standard (AES) removes loopholes.In AES Encryption algorithm Sub Bytes transformation utilizes S-Box. The subordinate Bytes replacement could be a nonlinear Byte replacement that utilizes substitution table (i.e. S-Box) takes the multiplicative inverse (GF (2 8)) and implies an affine transform to do the Sub Bytes transformation. In this research work I explored substitution table, multiplicative inverse and affine transform mathematics in Galois field; besides I recommended an encryption table to further encode the yield information.
2nd International Conference on Innovations in Electronics, Signal Processing and Communication (IESC), 2019
In this paper, a high speed and low power XOR-XNOR circuit in hybrid logic style in 90 nm CMOS te... more In this paper, a high speed and low power XOR-XNOR circuit in hybrid logic style in 90 nm CMOS technology is presented. The proposed XOR-XNOR circuit is symmetrical and has only single pass transistor in all delay paths. The designed circuit provides simultaneous generation of XOR-XNOR logic, balanced output and exhibits full voltage swing in all internal and external nodes. Due to full swing in delay path, the circuit has high portability, high noise robustness, and good driving capabilities. The simulation results show 8%, 5%, and 13.2% improvement in delay, power consumption and Power Delay Product (PDP), respectively. The circuit has used only 10 transistors.