rust (original) (raw)

This extends currently clobber-only vector registers (vreg) support to allow passing #[repr(simd)] types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output.

This is unstable and gated under new #![feature(asm_experimental_reg)] (tracking issue: #133416). If the feature is not enabled, only clober is supported as before.

Architecture	Register class	Target feature	Allowed types
s390x	vreg	vector	i32, f32, i64, f64, i128, f128, i8x16, i16x8, i32x4, i64x2, f32x4, f64x2

This matches the list of types that are supported by the vector registers in LLVM:
https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313

In addition to core::simd types and floats listed above, custom #[repr(simd)] types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable.

Currently there is no SIMD type for s390x in core::arch, but this is tracked in #130869.

cc #130869 about vector facility support in s390x
cc #125398 & #116909 about f128 support in asm

@rustbot label +O-SystemZ +A-inline-assembly