Robbie Vincke | IMEC - Academia.edu (original) (raw)

Papers by Robbie Vincke

Optics Express, 2021

This paper presents a passive autofocus algorithm applicable to interferometric microscopes. The ... more This paper presents a passive autofocus algorithm applicable to interferometric microscopes. The proposed algorithm uses the number of slope variations in an image mask to locate the focal plane (based on focus-inflection points) and identify the two neighboring planes at which fringes respectively appear and disappear. In experiments involving a Mirau objective lens, the proposed algorithm matched the autofocusing performance of conventional algorithms, and significantly outperformed detection schemes based on zero-order interference fringe in dealing with all kinds of surface blemish, regardless of severity. In experiments, the proposed algorithm also proved highly effective in cases without fringes.

The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the stren... more The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the strengths of an FPGA and a general purpose processor on one chip does not only simplify PCB layout, it also removes the communication bottleneck between processor and FPGA. Moreover, it allows the designer to partition applications and map parts of an application to either programmable logic or processing system. A case study on a voice-over-ethernet system illustrates partitioning by means of the processing requirements. This partitioning is called the Planar Design Pattern. Management of the communication channel is done by one of the processor cores. While high-speed data streaming itself is done in programmable logic.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for a transition to a multicore environment. Parallel design patterns, such as Map Reduce, Task Graph, Thread Pool, Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust application can be obtained. The key issues for concurrent calculation of a Fast Fourier Transform are determined at a higher level avoiding low-level patch-ups.

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading parti... more Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. The concept is analogue to a processor context switch. System Flexibility: When a specific part of a design needs to be reconfigured it is sometimes necessary to preserve the existing communication link instead of resetting the full device. Size and Cost Reduction: Some function are time-mutual exclusive to each other. This means some functions never need to exists on the same time. Instead of implementing all functions in parallel and selecting the needed function using a multiplexer, PR can dynamically change the needed function. Power Reduction: In embedded systems where power efficiency is an issue. Some functions can be reconfigured with a blank bitstream to save power consumption. Also multiple versions of the same function can be made. A high-end implementation consuming a lot of power and a minimal ...

In the embedded world, symmetric multiprocessing architectures are currently most popular, howeve... more In the embedded world, symmetric multiprocessing architectures are currently most popular, however more embedded hardware platforms are being developed with asymmetric multiprocessor architectures. These may enable higher performance and provide cleaner separation of subsystems. Telecom applications are typically designed applying a planar architecture pattern. The goal of our experiments is to compare the performance and cross-plane influence in dualcore symmetric and asymmetric multiprocessing environments. Next to a pronounced performance difference, a crossinfluence between the different planes has been verified.

2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2014

ABSTRACT Writing parallel software effectively for embedded systems is not an easy task. We belie... more ABSTRACT Writing parallel software effectively for embedded systems is not an easy task. We believe a new approach is needed to maximize the performance speed-up. Therefore we propose a layered top-down model for parallel embedded software, based on Our Pattern Language for High-Performance Computing. Several case studies were developed to demonstrate the strength of the model. First, a Fast Fourier Transformation algorithm was parallelized using the top-down model. A speed-up was achieved close to the theoretical maximum. Next, a telecommunication system was migrated from a naive symmetric multiprocessing setup to an asymmetric multiprocessing set-up. Finally, an algorithm that searches for sequences in a list of arcs and lines was implemented in two different ways. The strengths and weaknesses of both parallel implementations are explained.

2013 Eighth International Conference on P2P, Parallel, Grid, Cloud and Internet Computing, 2013

Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concu... more Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concurrent software. Parallel Design Patterns can help in the migration process from legacy sequential to high-performing parallel code. Therefore we propose a layered model of parallel design patterns. When going through the layered model in a topdown approach, the developer is guided through the transition from sequential to parallel code. The value of the layered model is shown using a cycle/chain-detection algorithm. Two different design pattern approaches are used in order to compare performance impact. First, an application is implemented with a minimum on algorithm modifications using the Map-Reduce design pattern. Next, the same algorithm is rewritten using the graph theory.

Typical telecom applications apply a planar architecture pattern based on the processing requirem... more Typical telecom applications apply a planar architecture pattern based on the processing requirements of each subsystem. In a symmetric multiprocessing environment all applications share the same hardware resources. However, currently embedded hardware platforms are being designed with asymmetric multiprocessor architectures to improve separation and increase performance of noninterfering tasks. These asymmetric multiprocessor architectures allow different planes to be separated and assign dedicated hardware for each responsibility. While planes are logically separated, some hardware is still shared and creates cross-plane influence effects which will impact the performance of the system. The aim of this report is to evaluate, in an embedded environment, the performance of a typical symmetric multiprocessing architecture compared to its asymmetric multiprocessing variant, applied on a telecom application.

Multicore architectures are becoming available in embedded systems. However, parallelizing sequen... more Multicore architectures are becoming available in embedded systems. However, parallelizing sequential software is a challenging task. A structured approach is needed to exploit parallel opportunities. Therefore we propose a top- down approach based on a layered model of parallel design patterns. As a proof of concept this approach has been applied on a number of algorithms including the Fast Fourier Transformation. The FFT algorithm has been implemented parallel on a Linux based embedded system while others were implemented in a freestanding environment. Keywords - Multicore embedded systems, design patterns, parallelizing sequential code, FFT

status: published, 2012

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the primary reasons to adopt a multicore embedded system. Yet, the challenge is to write optimal performing software, especially in an environment which lacks the aid of an Operating System. Parallel design patterns, such as Fork/Join and Thread Pool, assist to implement or migrate to a multicore embedded application. In our experiments, a computational intensive example is implemented and thoroughly ...

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading parti... more Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. The concept is analogue to a processor context switch. -System Flexibility: When a specific part of a design needs to be reconfigured it is sometimes necessary to preserve the existing communication link instead of resetting the full device.

Writing parallel software effectively for embedded systems is not an easy task. We believe a new ... more Writing parallel software effectively for embedded systems is not an easy task. We believe a new approach is needed to maximize the performance speed-up. Therefore we propose a layered top-down model for parallel embedded software, based on Our Pattern Language for High-Performance Computing. Several case studies were developed to demonstrate the strength of the model. First, a Fast Fourier Transformation algorithm was parallelized using the top-down model. A speed-up was achieved close to the theoretical maximum. Next, a telecommunication system was migrated from a naive symmetric multiprocessing setup to an asymmetric multiprocessing set-up. Finally, an algorithm that searches for sequences in a list of arcs and lines was implemented in two different ways. The strengths and weaknesses of both parallel implementations are explained.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for transition to a multicore environment. In most cases parallelization of existing algorithms is time consuming and error prone, dealing with low-level constructs. Migrating principles of object-oriented design patterns to parallel embedded software avoids this. We propose a top-down approach for refactoring existing sequential to parallel algorithms in an intuitive way, avoiding the usage of locking mechanisms. We illustrate the approach on the well known Fast Fourier Transformation algorithm. Parallel design patterns, such as Map Reduce, Divide-and-Conquer and Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust and better performing application is obtained.

Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concu... more Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concurrent software. Parallel Design Patterns can help in the migration process from legacy sequential to high-performing parallel code. Therefore we propose a layered model of parallel design patterns. When going through the layered model in a topdown approach, the developer is guided through the transition from sequential to parallel code. The value of the layered model is shown using a cycle/chain-detection algorithm. Two different design pattern approaches are used in order to compare performance impact.

In the embedded world, symmetric multiprocessing architectures are currently most popular, howeve... more In the embedded world, symmetric multiprocessing architectures are currently most popular, however more embedded hardware platforms are being developed with asymmetric multiprocessor architectures. These may enable higher performance and provide cleaner separation of subsystems. Telecom applications are typically designed applying a planar architecture pattern. The goal of our experiments is to compare the performance and cross-plane influence in dualcore symmetric and asymmetric multiprocessing environments. Next to a pronounced performance difference, a crossinfluence between the different planes has been verified.

The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the stren... more The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the strengths of an FPGA and a general purpose processor on one chip does not only simplify PCB layout, it also removes the communication bottleneck between processor and FPGA. Moreover, it allows the designer to partition applications and map parts of an application to either programmable logic or processing system. A case study on a voice-over-ethernet system illustrates partitioning by means of the processing requirements. This partitioning is called the Planar Design Pattern. Management of the communication channel is done by one of the processor cores. While high-speed data streaming itself is done in programmable logic.

Typical telecom applications apply a planar architecture pattern based on the processing requirem... more Typical telecom applications apply a planar architecture pattern based on the processing requirements of each subsystem. In a symmetric multiprocessing environment all applications share the same hardware resources. However, currently embedded hardware platforms are being designed with asymmetric multiprocessor architectures to improve separation and increase performance of noninterfering tasks. These asymmetric multiprocessor architectures allow different planes to be separated and assign dedicated hardware for each responsibility. While planes are logically separated, some hardware is still shared and creates cross-plane influence effects which will impact the performance of the system. The aim of this report is to evaluate, in an embedded environment, the performance of a typical symmetric multiprocessing architecture compared to its asymmetric multiprocessing variant, applied on a telecom application.

Multicore architectures are becoming available in embedded systems. However, parallelizing sequen... more Multicore architectures are becoming available in embedded systems. However, parallelizing sequential software is a challenging task. A structured approach is needed to exploit parallel opportunities. Therefore we propose a topdown approach based on a layered model of parallel design patterns. As a proof of concept this approach has been applied on a number of algorithms including the Fast Fourier Transformation.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for a transition to a multicore environment. Parallel design patterns, such as Map Reduce, Task Graph, Thread Pool, Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust application can be obtained.

Optics Express, 2021

This paper presents a passive autofocus algorithm applicable to interferometric microscopes. The ... more This paper presents a passive autofocus algorithm applicable to interferometric microscopes. The proposed algorithm uses the number of slope variations in an image mask to locate the focal plane (based on focus-inflection points) and identify the two neighboring planes at which fringes respectively appear and disappear. In experiments involving a Mirau objective lens, the proposed algorithm matched the autofocusing performance of conventional algorithms, and significantly outperformed detection schemes based on zero-order interference fringe in dealing with all kinds of surface blemish, regardless of severity. In experiments, the proposed algorithm also proved highly effective in cases without fringes.

The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the stren... more The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the strengths of an FPGA and a general purpose processor on one chip does not only simplify PCB layout, it also removes the communication bottleneck between processor and FPGA. Moreover, it allows the designer to partition applications and map parts of an application to either programmable logic or processing system. A case study on a voice-over-ethernet system illustrates partitioning by means of the processing requirements. This partitioning is called the Planar Design Pattern. Management of the communication channel is done by one of the processor cores. While high-speed data streaming itself is done in programmable logic.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for a transition to a multicore environment. Parallel design patterns, such as Map Reduce, Task Graph, Thread Pool, Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust application can be obtained. The key issues for concurrent calculation of a Fast Fourier Transform are determined at a higher level avoiding low-level patch-ups.

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading parti... more Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. The concept is analogue to a processor context switch. System Flexibility: When a specific part of a design needs to be reconfigured it is sometimes necessary to preserve the existing communication link instead of resetting the full device. Size and Cost Reduction: Some function are time-mutual exclusive to each other. This means some functions never need to exists on the same time. Instead of implementing all functions in parallel and selecting the needed function using a multiplexer, PR can dynamically change the needed function. Power Reduction: In embedded systems where power efficiency is an issue. Some functions can be reconfigured with a blank bitstream to save power consumption. Also multiple versions of the same function can be made. A high-end implementation consuming a lot of power and a minimal ...

In the embedded world, symmetric multiprocessing architectures are currently most popular, howeve... more In the embedded world, symmetric multiprocessing architectures are currently most popular, however more embedded hardware platforms are being developed with asymmetric multiprocessor architectures. These may enable higher performance and provide cleaner separation of subsystems. Telecom applications are typically designed applying a planar architecture pattern. The goal of our experiments is to compare the performance and cross-plane influence in dualcore symmetric and asymmetric multiprocessing environments. Next to a pronounced performance difference, a crossinfluence between the different planes has been verified.

2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, 2014

ABSTRACT Writing parallel software effectively for embedded systems is not an easy task. We belie... more ABSTRACT Writing parallel software effectively for embedded systems is not an easy task. We believe a new approach is needed to maximize the performance speed-up. Therefore we propose a layered top-down model for parallel embedded software, based on Our Pattern Language for High-Performance Computing. Several case studies were developed to demonstrate the strength of the model. First, a Fast Fourier Transformation algorithm was parallelized using the top-down model. A speed-up was achieved close to the theoretical maximum. Next, a telecommunication system was migrated from a naive symmetric multiprocessing setup to an asymmetric multiprocessing set-up. Finally, an algorithm that searches for sequences in a list of arcs and lines was implemented in two different ways. The strengths and weaknesses of both parallel implementations are explained.

2013 Eighth International Conference on P2P, Parallel, Grid, Cloud and Internet Computing, 2013

Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concu... more Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concurrent software. Parallel Design Patterns can help in the migration process from legacy sequential to high-performing parallel code. Therefore we propose a layered model of parallel design patterns. When going through the layered model in a topdown approach, the developer is guided through the transition from sequential to parallel code. The value of the layered model is shown using a cycle/chain-detection algorithm. Two different design pattern approaches are used in order to compare performance impact. First, an application is implemented with a minimum on algorithm modifications using the Map-Reduce design pattern. Next, the same algorithm is rewritten using the graph theory.

Typical telecom applications apply a planar architecture pattern based on the processing requirem... more Typical telecom applications apply a planar architecture pattern based on the processing requirements of each subsystem. In a symmetric multiprocessing environment all applications share the same hardware resources. However, currently embedded hardware platforms are being designed with asymmetric multiprocessor architectures to improve separation and increase performance of noninterfering tasks. These asymmetric multiprocessor architectures allow different planes to be separated and assign dedicated hardware for each responsibility. While planes are logically separated, some hardware is still shared and creates cross-plane influence effects which will impact the performance of the system. The aim of this report is to evaluate, in an embedded environment, the performance of a typical symmetric multiprocessing architecture compared to its asymmetric multiprocessing variant, applied on a telecom application.

Multicore architectures are becoming available in embedded systems. However, parallelizing sequen... more Multicore architectures are becoming available in embedded systems. However, parallelizing sequential software is a challenging task. A structured approach is needed to exploit parallel opportunities. Therefore we propose a top- down approach based on a layered model of parallel design patterns. As a proof of concept this approach has been applied on a number of algorithms including the Fast Fourier Transformation. The FFT algorithm has been implemented parallel on a Linux based embedded system while others were implemented in a freestanding environment. Keywords - Multicore embedded systems, design patterns, parallelizing sequential code, FFT

status: published, 2012

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the primary reasons to adopt a multicore embedded system. Yet, the challenge is to write optimal performing software, especially in an environment which lacks the aid of an Operating System. Parallel design patterns, such as Fork/Join and Thread Pool, assist to implement or migrate to a multicore embedded application. In our experiments, a computational intensive example is implemented and thoroughly ...

Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading parti... more Partial Reconfiguration is the ability to dynamically modify blocks of logic by downloading partial bit files while the remaining logic continues to operate without interruption. The concept is analogue to a processor context switch. -System Flexibility: When a specific part of a design needs to be reconfigured it is sometimes necessary to preserve the existing communication link instead of resetting the full device.

Writing parallel software effectively for embedded systems is not an easy task. We believe a new ... more Writing parallel software effectively for embedded systems is not an easy task. We believe a new approach is needed to maximize the performance speed-up. Therefore we propose a layered top-down model for parallel embedded software, based on Our Pattern Language for High-Performance Computing. Several case studies were developed to demonstrate the strength of the model. First, a Fast Fourier Transformation algorithm was parallelized using the top-down model. A speed-up was achieved close to the theoretical maximum. Next, a telecommunication system was migrated from a naive symmetric multiprocessing setup to an asymmetric multiprocessing set-up. Finally, an algorithm that searches for sequences in a list of arcs and lines was implemented in two different ways. The strengths and weaknesses of both parallel implementations are explained.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for transition to a multicore environment. In most cases parallelization of existing algorithms is time consuming and error prone, dealing with low-level constructs. Migrating principles of object-oriented design patterns to parallel embedded software avoids this. We propose a top-down approach for refactoring existing sequential to parallel algorithms in an intuitive way, avoiding the usage of locking mechanisms. We illustrate the approach on the well known Fast Fourier Transformation algorithm. Parallel design patterns, such as Map Reduce, Divide-and-Conquer and Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust and better performing application is obtained.

Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concu... more Multi-core systems are becoming mainstream. However, it is still a big challenge to develop concurrent software. Parallel Design Patterns can help in the migration process from legacy sequential to high-performing parallel code. Therefore we propose a layered model of parallel design patterns. When going through the layered model in a topdown approach, the developer is guided through the transition from sequential to parallel code. The value of the layered model is shown using a cycle/chain-detection algorithm. Two different design pattern approaches are used in order to compare performance impact.

In the embedded world, symmetric multiprocessing architectures are currently most popular, howeve... more In the embedded world, symmetric multiprocessing architectures are currently most popular, however more embedded hardware platforms are being developed with asymmetric multiprocessor architectures. These may enable higher performance and provide cleaner separation of subsystems. Telecom applications are typically designed applying a planar architecture pattern. The goal of our experiments is to compare the performance and cross-plane influence in dualcore symmetric and asymmetric multiprocessing environments. Next to a pronounced performance difference, a crossinfluence between the different planes has been verified.

The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the stren... more The rising demand for high-performing embedded systems made FPGAs ubiquitous. Combining the strengths of an FPGA and a general purpose processor on one chip does not only simplify PCB layout, it also removes the communication bottleneck between processor and FPGA. Moreover, it allows the designer to partition applications and map parts of an application to either programmable logic or processing system. A case study on a voice-over-ethernet system illustrates partitioning by means of the processing requirements. This partitioning is called the Planar Design Pattern. Management of the communication channel is done by one of the processor cores. While high-speed data streaming itself is done in programmable logic.

Typical telecom applications apply a planar architecture pattern based on the processing requirem... more Typical telecom applications apply a planar architecture pattern based on the processing requirements of each subsystem. In a symmetric multiprocessing environment all applications share the same hardware resources. However, currently embedded hardware platforms are being designed with asymmetric multiprocessor architectures to improve separation and increase performance of noninterfering tasks. These asymmetric multiprocessor architectures allow different planes to be separated and assign dedicated hardware for each responsibility. While planes are logically separated, some hardware is still shared and creates cross-plane influence effects which will impact the performance of the system. The aim of this report is to evaluate, in an embedded environment, the performance of a typical symmetric multiprocessing architecture compared to its asymmetric multiprocessing variant, applied on a telecom application.

Multicore architectures are becoming available in embedded systems. However, parallelizing sequen... more Multicore architectures are becoming available in embedded systems. However, parallelizing sequential software is a challenging task. A structured approach is needed to exploit parallel opportunities. Therefore we propose a topdown approach based on a layered model of parallel design patterns. As a proof of concept this approach has been applied on a number of algorithms including the Fast Fourier Transformation.

Multicore embedded systems introduce new opportunities and challenges. Scaling of computational p... more Multicore embedded systems introduce new opportunities and challenges. Scaling of computational power is one of the main reasons for a transition to a multicore environment. Parallel design patterns, such as Map Reduce, Task Graph, Thread Pool, Task Parallelism assist to derive a parallel approach for calculating the Fast Fourier Transform. By combining these design patterns, a robust application can be obtained.