A. Annema - Academia.edu (original) (raw)

Papers by A. Annema

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009

The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor wo... more The bulk CMOS technology is expected to scale down to about 32nm node and likely the successor would be the FinFET. The FinFET is an ultra-thin body multi-gate MOS transistor with among other characteristics a much higher voltage gain compared to a conventional bulk MOS transistor [1]. Bandgap reference circuits cannot be directly ported from bulk CMOS technologies to SOI FinFET technologies, because both conventional diodes cannot be realized in thin SOI layers and also, area-efficient resistors are not readily available in processes with only metal(lic) gates. In this paper, a sub-1V bandgap reference circuit is implemented in a 32nm SOI FinFET technology, with an architecture that significantly reduces the required total resistance value.

Journal of Applied Physics, 2015

This work presents the modeling of light emission from silicon based p þ n junctions operating in... more This work presents the modeling of light emission from silicon based p þ n junctions operating in avalanche breakdown. We revisit the photon emission process under the influence of relatively high electric fields in a reverse biased junction (>10 5 V/cm). The photon emission rate is described as a function of the electron temperature T e , which is computed from the spatial distribution of the electric field. The light emission spectra lie around the visible spectral range (k $ 300-850 nm), where the peak wavelength and the optical intensity are both doping level dependent. It is theoretically derived that a specific minimum geometrical width ($170 nm) of the active region of avalanche is required, corresponding to a breakdown voltage of $5 V, below which the rate of photon emission in the desired spectrum drops. The derived model is validated using experimental data obtained from ultra-shallow p þ n junctions with low absorption through a nm-thin p þ region and surface coverage of solely 3 nm of pure boron. We observe a peak in the emission spectra near 580 nm and 650 nm for diodes with breakdown voltages 7 V and 14 V, respectively, consistent with our model. V

$Research paper thumbnail of A Radiation Hard Bandgap Reference Circuit in a Standard 0.13 <formula> <tex>$\mu$</tex></formula>m CMOS Technology$

IEEE Transactions on Nuclear Science, 2007

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increas... more With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOS devices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV (= 6 mV chip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si).

IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 2003

Analyses of the influence of different geometries (layouts) and structures of high-speed CMOS pho... more Analyses of the influence of different geometries (layouts) and structures of high-speed CMOS photodiodes on their intrinsic (physical) and electrical bandwidths are presented. Three photodiode structures are studied: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. According to the author's knowledge, this is a first time that the influence of various structures and geometries (layouts) of CMOS photodiodes on their bandwidth is analytically analysed.

2009 Proceedings of ESSCIRC, 2009

2012 IEEE International Solid-State Circuits Conference, 2012

A negative impedance is used to enable distortion cancellation between the transconductor and the... more A negative impedance is used to enable distortion cancellation between the transconductor and the cascode transistor for LNAs with a cascode topology. As a proof of concept, a resistive feedback LNA using this IM3 cancellation technique in a standard 0.16µm CMOS process shows that for 0.1GHz to 1GHz, improvements of 6.3dB to 10dB for IIP3 and 0.2dB to 1dB for gain are achieved without noise degradation. The power consumption for the LNA is increased by 2%, and the die area by about 700µm 2 .

A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nom... more A circuit technique for RF power amplifiers that reliably handle voltage peaks well above the nominal supply voltage is presented. To achieve this high-voltage tolerance the circuit implements switched-cascode transistors that yield reliable operation for voltages up to 7V at RF frequencies in a 2.5V CMOS process. Advantages of this include the possibility to use higherohmic load resistors. The impact

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2014

Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, 2000

A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technolog... more A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is

Key Engineering Materials, 2004

Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 2003

A high-performance lateral polysilicon photodiode was designed in standard 0.18 μm CMOS technolog... more A high-performance lateral polysilicon photodiode was designed in standard 0.18 μm CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which figure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is

The authors propose a robust curve trac ing scheme for the simulation of the com plete Ic(VcE)I... more The authors propose a robust curve trac ing scheme for the simulation of the com plete Ic(VcE)I In=o breakdown characteris tic of a bipolar transistor including snap

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013

ABSTRACT A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS t... more ABSTRACT A two-times interleaved DAC using only a single supply voltage in a standard 65nm CMOS technology is presented. The interleaving architecture suppresses most of the non-idealities commonly found in high-speed DACs. Spurs generated by the interleaved architecture are suppressed by a novel calibration algorithm. The design achieves IM3 levels below -62dB across Nyquist with a clock frequency of 1.7GHz. The circuit's active area is 0.4mm2 and the power consumption is 70mW from a nominal 1.2V supply.

Optics express, Jan 7, 2013

For hybrid integration of an optical chip with an electronic chip containing photo-diodes and pro... more For hybrid integration of an optical chip with an electronic chip containing photo-diodes and processing electronics, light must be coupled from the optical to the electronic chip. This paper presents a method to fabricate quasi-total-internal-reflecting mirrors on an optical chip, placed at an angle of 45° with the chip surface, that enable 90° out-of-plane light coupling between flip-chip bonded chips. The fabrication method utilizes a metal-free, parallel process and is fully compatible with conventional fabrication of optical chips. The mirrors are created using anisotropic etching of 45° facets in a Si substrate, followed by fabrication of the optical structures. After removal of the mirror-defining Si structures by isotropic etching, the obtained interfaces between optical structure and air direct the output from optical waveguides to out-of-plane photo-detectors on the electronic chip, which is aimed to be flip-chip mounted on the optical chip. For transverse-electric (transv...

Robust high-voltage tolerant U 0 that do not need process options is presented, demonstrated on 5... more Robust high-voltage tolerant U 0 that do not need process options is presented, demonstrated on 5.5V tolerant opendrain U 0 in a 2.5V 0 . 2 5~ CMOS technology. Circuit techniques limit oxide stress and hot-carrier degradation, resulting in hundreds of years extrapolated lifetime for 5.5V pad voltage swing, 2.2V supply voltage, lOMHz switching frequency. The shown concepts are also implemented in other types of U 0 and can easily be scaled towards newer processes.

Microelectronics Reliability, 2005

This paper analyzes the bandwidth of high-speed photodiodes in a fully standard 0.18μm CMOS techn... more This paper analyzes the bandwidth of high-speed photodiodes in a fully standard 0.18μm CMOS technology for the CD/DVD optical pick-up units. Three diode structures are investigated: nwell/p-substrate, p+/nwell/p-substrate and p+/nwell. The photodiode performances are compared for λ=780nm and λ=650nm wavelength, corresponding to the lasers for CD and DVD, respectively. Slow substrate photocurrent component limits the bandwidth of nwell/p-substrate and p+/nwell/p-substrate

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004

This paper introduces a recursive multibit architecture that enables a high effective quantizer r... more This paper introduces a recursive multibit architecture that enables a high effective quantizer resolution while needing only a limited number of DAC elements. The recursive architecture consists of a set of modulators, whereby each stage cancels the quantization noise of the preceding stage. Conventional DEM algorithms can be used in each stage to reduce the sensitivity to mismatch. The architecture enables a significant reduction of both the signal-band and out-of-band quantization noise power, compared to conventional multibit converters.