A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior (original) (raw)
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The impact of CMOS scaling projected on a 6b full-Nyquist non-calibrated flash ADC
A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performance of a non-calibrated flash ADC is directly related to device properties; a scaling analysis of our ADC in and across CMOS technologies gives insight into the excellent usability of 45nm technology for AD converter design.
Limitations of Switched-Capacitor Analog/Digital Converters with Reference Processing Units
Frequenz, 1993
This paper discusses the major limitations of an emerging new class of A/D converters (ADC's), namely those employing a separate reference processing unit (RPU) which is linked to a signal processing unit (SPU). Three circuits are basically investigated; the first is by Chen and Svensson [1], the second is by Yung and Chao [2], and the third is a modified version of the first with a novel RPU. The effects of the following parameters are investigated: op-amp dc gain, capacitor ratio-mismatch error, and charge injection of switches. These effects are assessed in terms of their corresponding absolute integral nonlinearity (INL). Pertinent formulae are derived, and the results of computer simulations are presented. Whenever possible, comparison is held among the circuits presented. Übersicht: Dieser Beitrag beschreibt die Grenzen eines neuen Typs von A/D-Umsetzern mit einem getrennten Referenzspannungsprozessor (RPU), der mit einer Signalprozessoreinheit (SPU) verbunden ist. Drei Schaltungen werden grundsätzlich untersucht. Die erste stammt von Chen und Svensson [1], die zweite von Yung und Chap [2], die dritte ist eine modifizierte Version der ersten mit einer neuartigen RPU. Die Auswirkungen folgender Parameter werden untersucht: Gleichspannungsverstärkung des Operationsverstärkers, Abweichungen im Kapazitätsverhältnis und von Schaltern verursachte Ladungsänderungen. Der Einfluß dieser Effekte auf die entsprechende Integrale Nichtlinearität (INL) wird dargestellt. Soweit möglich werden die Schaltungen miteinander verglichen.
Digitized preamplifiers: a circuit structure for sliding-scale optimization of the ADC range
IEEE Transactions on Nuclear Science, 2006
This work deals with the digitization of chargepreamplifier waveforms obtained from X-ray and-ray sensors. We suggest that the well-known "sliding-scale correction" structure can be inserted into a negative-feedback control loop to cancel the signal walks brought about by event pileup, low-frequency disturbances, microphonism, and hum. Cancellation of the walks permits to use the full analog-to-digital converter (ADC) range for the signals, even in high event rate conditions. The signal distortion caused by such cancellation is then eliminated numerically by the sliding-scale mechanism. As a result an extended dynamic range is obtained. Using a 12-bit ADC we got two extra bits to accomodate the baseline walks and 1.14 to 1.43 extra bits on individual signals with 0.1 to 1 s rise time.
A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination
IEEE Journal of Solid-State Circuits, 2002
The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-m CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.
Embedded 240-MW 10-B 50-MS/S CMOS ADC in 1-MM **2
Csi, 1999
A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity (DNL) and 2 b in integral nonlinearity (INL) in a flash analog-to-digital converter (ADC). Fabricated in a 0.5-m, triple-metal, singlepoly CMOS process, the circuit measures 1.4 mm 2 1.4 mm including a bandgap and a sample-and-hold (SH), while the ADC itself occupies 1-mm 2. At a conversion rate of 50-MS/s the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB S=(N + D) with a 12-MHz 90% full-scale input.
A 6-b 1.6-Gsample/s Flash ADC in 0.18-mum CMOS Using Averaging Termination
Ieee J Solid State Circuits, 2002
The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-m CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.
A 10-b 20-Msample/s low-power CMOS ADC
IEEE Journal of Solid-State Circuits, 1995
Absfruct-A single-ended input but internally differential 10 b, 20 Msamplds pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer ampliers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 pm CMOS technology exhibits a DNL of f0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm'.
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
IEEE Journal of Solid-State Circuits, 2005
An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 m CMOS process, achieves 77-dB SFDR at 0.9 V and 5 MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm 2. Index Terms-Algorithmic ADC, background digital calibration, low power, low voltage, pipelined ADC, two channel ADC architecture.
2012
Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.