A. Tangel - Academia.edu (original) (raw)
Papers by A. Tangel
Wireless Personal Communications, 2011
For the integration of smart antennas into third generation code division multiple access (CDMA) ... more For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming 123 S. Dikmese et al.
2013 18th International Conference on Digital Signal Processing (DSP), 2013
ABSTRACT In this study, an improved, time sample cross correlation based power attack is applied ... more ABSTRACT In this study, an improved, time sample cross correlation based power attack is applied on a Montgomery Ladder implementation of the RSA. In the attack, by using an implementation level property, power traces related to the all key bits are cross correlated with each other and resulting correlation values are summed and compared to a threshold to estimate the secret key of the target RSA implementation. The attack could retrieve all the key bits by using 75% lesser power traces when compared to the single fixed reference bit and 50% lesser power traces compared to the double fixed reference bits approaches which are applied on the same implementation earlier.
2013 3rd IEEE International Advance Computing Conference (IACC), 2013
ABSTRACT In this study, two novel time sample cross correlation based power attacks using novel v... more ABSTRACT In this study, two novel time sample cross correlation based power attacks using novel voting mechanism and novel multi reference bit mechanism are introduced. These two attack methods are applied on a Montgomery Ladder (ML) implementation of RSA algorithm. In the target ML implementation, use of operands from different locations according to the existence of toggling on the exponent bits is the source of vulnerability. To retrieve the bit type (toggling or not toggling of consecutive bit values) of the secret key, cross correlation values between power traces of a fixed reference bit and power trace of remaining bits of the secret key are calculated. For proposed first method, for each key bit, if this cross correlation value is greater than a threshold, this bit is labeled as the same type, otherwise labeled as the opposite type with respect to the reference bit and corresponding scores are increased. This procedure is repeated for each RSA run. As the number of used power traces are increased, to decide to the final type of each key bit, a voting mechanism is applied on the scores gathered from each RSA run. By application of this method, type of 970 bits of the 1024 bit RSA key could be retrieved correctly. However locations of wrongly estimated 54 bit positions can be found by examining the corresponding scores of those bits. For the second method, instead of scores, sum of correlation values are used to decide to the type of each bit. By this method type of all the 1024 key bits could be estimated correctly. It is also shown that this second attack method can be improved by using multi reference bits together. This property makes the method more flexible. Both of the attack methods are not affected by message blinding or modulus blinding type countermeasures. For a successful attack of these types, positions of square and multiply operations related with each key bit must be known. However, exponent blinding can be used as a countermeasure.
The main purpose of this study is to employ the so-called TIQ technique in a traditional CMOS fol... more The main purpose of this study is to employ the so-called TIQ technique in a traditional CMOS folding ADC. It also has a novel approach when multiplexing the appropriate folded signals into the fine flash part of the converter. The simulation results include 1MHz analog input bandwidth with 250 Ms/s sampling rate using AMIS 0.5 micron CMOS process model parameters. The analog range is 1.5V, power supply is 3.3V.
EUROCON 2005 - The International Conference on "Computer as a Tool", 2005
In this article, a novel 10-bit two-step Flash A/D converter architecture based on the threshold ... more In this article, a novel 10-bit two-step Flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented. The simulation results include 1.5V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s. The process parameter and temperature variation analysis of the converter is especially included. The DC simulation results show linearity measures of less than 0.1 LSB DNL and INL for each 5-bit flash core. The active chip area is 1.4mm2 in 0.5,u CMOS technology.
IET Microwaves, Antennas & Propagation, 2010
Software radio implementations of beamformers on programmable processors such as digital signal p... more Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP-and FPGA-based implementations of space -code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Du ¼ 28, whereas it can be achieved within less than 25 ms on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.
The purpose of this work is to employ the so-called Threshold Inverter Quantization (TIQ) techniq... more The purpose of this work is to employ the so-called Threshold Inverter Quantization (TIQ) technique in traditional CMOS folding ADC architectures. It also has a novel approach when multiplexing the appropriate folded signals into the fine flash part of the converter. The simulation results include 1MHz analogue input bandwidth, 1 Gs/s sampling rate using AMS-HIT KIT design library for 0.35µ H35B4 CMOS process model parameters. The analogue range is 1.7V, power supply is 3.3V, and maximum power consumption is 375mW. This paper also focuses on practical design considerations of the analogue pre-processing unit in folding ADCs.
Abstract: - This paper presents a calibrator circuit to minimize mainly the process parameter var... more Abstract: - This paper presents a calibrator circuit to minimize mainly the process parameter variations related problems of TIQ Based Flash ADC designs. The simulations are carried out using 0.35μ CMOS technology in two directions; to correct the input analog range deviations, ...
This paper presents design and implementation of a multiple-output 48 kHz PWM-controlled pulse ge... more This paper presents design and implementation of a multiple-output 48 kHz PWM-controlled pulse generator for ultrasonic cleaning machines. The complete digital part including frequency and PWM-controlled pulse generator and display driver unit to drive four independent ultrasonic power units has been implemented on a single FPGA core. As a result, more precise (5Hz step) frequency adjustment and four independent but
Wireless Personal Communications, 2011
For the integration of smart antennas into third generation code division multiple access (CDMA) ... more For the integration of smart antennas into third generation code division multiple access (CDMA) base stations, it still remains as a challenging task to implement smart antenna algorithms on programmable processors. In this paper, we study implementations of some CDMA compatible beamforming algorithms, namely least mean square (LMS), constant modulus (CM), and space code correlator (SCC) algorithms, using Xilinx's Virtex family FPGAs. This study exhibits feasibility of implementing even simple, practical, and computationally small algorithms based on today's most powerful FPGA technologies. 16 and 32 bits floating point implementations of the algorithms are investigated using both Virtex II and Virtex IV FPGAs. CDMA2000 reverse link baseband signal format is used in the signal modeling. Randomly changing fading and Direction-of-arrivals (DOAs) of multipaths are considered as a channel condition. The implementation results in terms of beamforming 123 S. Dikmese et al.
2013 18th International Conference on Digital Signal Processing (DSP), 2013
ABSTRACT In this study, an improved, time sample cross correlation based power attack is applied ... more ABSTRACT In this study, an improved, time sample cross correlation based power attack is applied on a Montgomery Ladder implementation of the RSA. In the attack, by using an implementation level property, power traces related to the all key bits are cross correlated with each other and resulting correlation values are summed and compared to a threshold to estimate the secret key of the target RSA implementation. The attack could retrieve all the key bits by using 75% lesser power traces when compared to the single fixed reference bit and 50% lesser power traces compared to the double fixed reference bits approaches which are applied on the same implementation earlier.
2013 3rd IEEE International Advance Computing Conference (IACC), 2013
ABSTRACT In this study, two novel time sample cross correlation based power attacks using novel v... more ABSTRACT In this study, two novel time sample cross correlation based power attacks using novel voting mechanism and novel multi reference bit mechanism are introduced. These two attack methods are applied on a Montgomery Ladder (ML) implementation of RSA algorithm. In the target ML implementation, use of operands from different locations according to the existence of toggling on the exponent bits is the source of vulnerability. To retrieve the bit type (toggling or not toggling of consecutive bit values) of the secret key, cross correlation values between power traces of a fixed reference bit and power trace of remaining bits of the secret key are calculated. For proposed first method, for each key bit, if this cross correlation value is greater than a threshold, this bit is labeled as the same type, otherwise labeled as the opposite type with respect to the reference bit and corresponding scores are increased. This procedure is repeated for each RSA run. As the number of used power traces are increased, to decide to the final type of each key bit, a voting mechanism is applied on the scores gathered from each RSA run. By application of this method, type of 970 bits of the 1024 bit RSA key could be retrieved correctly. However locations of wrongly estimated 54 bit positions can be found by examining the corresponding scores of those bits. For the second method, instead of scores, sum of correlation values are used to decide to the type of each bit. By this method type of all the 1024 key bits could be estimated correctly. It is also shown that this second attack method can be improved by using multi reference bits together. This property makes the method more flexible. Both of the attack methods are not affected by message blinding or modulus blinding type countermeasures. For a successful attack of these types, positions of square and multiply operations related with each key bit must be known. However, exponent blinding can be used as a countermeasure.
The main purpose of this study is to employ the so-called TIQ technique in a traditional CMOS fol... more The main purpose of this study is to employ the so-called TIQ technique in a traditional CMOS folding ADC. It also has a novel approach when multiplexing the appropriate folded signals into the fine flash part of the converter. The simulation results include 1MHz analog input bandwidth with 250 Ms/s sampling rate using AMIS 0.5 micron CMOS process model parameters. The analog range is 1.5V, power supply is 3.3V.
EUROCON 2005 - The International Conference on "Computer as a Tool", 2005
In this article, a novel 10-bit two-step Flash A/D converter architecture based on the threshold ... more In this article, a novel 10-bit two-step Flash A/D converter architecture based on the threshold inverter quantization technique, TIQ is presented. The simulation results include 1.5V analog input range, 30 MHz input bandwidth, and 250 mWatts of power consumption at maximum sampling rate of 500 Ms/s. The process parameter and temperature variation analysis of the converter is especially included. The DC simulation results show linearity measures of less than 0.1 LSB DNL and INL for each 5-bit flash core. The active chip area is 1.4mm2 in 0.5,u CMOS technology.
IET Microwaves, Antennas & Propagation, 2010
Software radio implementations of beamformers on programmable processors such as digital signal p... more Software radio implementations of beamformers on programmable processors such as digital signal processor (DSP) and field programmable gate array (FPGA) still remain as a challenge for the integration of smart antennas into existing wireless base stations for 3G systems. This study presents the comparison of DSP-and FPGA-based implementations of space -code correlator (SCC) beamformer, which is practical to use in CDMA2000 systems. Implementation methodology is demonstrated and results regarding beamforming accuracy, weight vector computation time (execution time) and resource utilisation are presented. The SCC algorithm is implemented on Texas Instruments (TI) TMS320C6713 floating-point digital signal processors (DSPs) and Xilinx's VirtexIV family FPGA. In signal modelling, CDMA2000 reverse link format is employed. The results show that beamformer weights can be obtained within less than 10 ms via implementation on c6713 DSP with direction-of-arrival (DOA) search resolution of Du ¼ 28, whereas it can be achieved within less than 25 ms on VirtexIV FPGA for five-element uniform linear array (ULA). These results demonstrate that FPGA implementation achieves weight vector computation in much smaller time (nearly 500 times) as compared to DSP implementation in this study.
The purpose of this work is to employ the so-called Threshold Inverter Quantization (TIQ) techniq... more The purpose of this work is to employ the so-called Threshold Inverter Quantization (TIQ) technique in traditional CMOS folding ADC architectures. It also has a novel approach when multiplexing the appropriate folded signals into the fine flash part of the converter. The simulation results include 1MHz analogue input bandwidth, 1 Gs/s sampling rate using AMS-HIT KIT design library for 0.35µ H35B4 CMOS process model parameters. The analogue range is 1.7V, power supply is 3.3V, and maximum power consumption is 375mW. This paper also focuses on practical design considerations of the analogue pre-processing unit in folding ADCs.
Abstract: - This paper presents a calibrator circuit to minimize mainly the process parameter var... more Abstract: - This paper presents a calibrator circuit to minimize mainly the process parameter variations related problems of TIQ Based Flash ADC designs. The simulations are carried out using 0.35μ CMOS technology in two directions; to correct the input analog range deviations, ...
This paper presents design and implementation of a multiple-output 48 kHz PWM-controlled pulse ge... more This paper presents design and implementation of a multiple-output 48 kHz PWM-controlled pulse generator for ultrasonic cleaning machines. The complete digital part including frequency and PWM-controlled pulse generator and display driver unit to drive four independent ultrasonic power units has been implemented on a single FPGA core. As a result, more precise (5Hz step) frequency adjustment and four independent but