Aidan Keady - Academia.edu (original) (raw)
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National Institute of Technology, Calicut
Graduate Center of the City University of New York
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Papers by Aidan Keady
European Solid-State Circuits Conference, 1999
This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for ... more This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for conversion of the IF signal. The architecture used is efficient in terms of silicon area usage and has improved performance over previous bandpass converters, allowing the IF to be at a higher frequency than the modulator clock rate. A chopping scheme is used to shift signals from the passband to DC and a lowpass modulator running at a decimated clockrate performs the A/D conversion. Simulation results, along with test results from an IC implementation of the converter, are presented to show the operation of the circuit and its use in radio receivers.
This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The I... more This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The IC is comprised of a Sigma-Delta A/D converter and a digital AM/FM demodulator. The Sigma Delta modulator converts the standard 10.7 MHz IF signal, allowing the use of digital channel-select filtering, providing improved performance over analog filtering. Subsequent demodulation and signal processing are performed digitally, allowing flexibility in the algorithms employed and greater integration with other digital circuitry in the system. There is also a software element to the system, as the stereo decoder and RDS decoding functions are implemented by DSP off-chip rather than on dedicated hardware. Behavioural-level simulations of the system are presented, which show it meets the requirements of 80 db SNR for stereo FM input signals over a 150 kHz bandwidth
Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL outpu... more Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL output signal resulting in a static phase offset. Classical analog approaches to reducing this offset consume large silicon area and increase gate leak- age mismatch. For ultra-deep-submicron (UDSM) technologies where gate leakage in- creases dramatically, reduction of static phase offset through digital calibration becomes more favorable. This paper presents a novel technique which digitally calibrates static phase offset down to < 10 ps for a PLL operating at 4.8 GHz, designed using a 1V 90nm CMOS process. Calibration is completed in only 2 steps, making the proposed technique suitable for systems requiring frequent switching such as frequency hopping systems commonly used in today’s wireless communication systems.
This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for ... more This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for conversion of the IF signal. The architecture used is efficient in terms of silicon area usage and has improved performance over previous bandpass converters, allowing the IF to be at a higher frequency than the modulator clock rate. A chopping scheme is used to shift signals from the passband to DC and a lowpass modulator running at a decimated clockrate performs the A/D conversion. Simulation results, along with test results from an IC implementation of the converter, are presented to show the operation of the circuit and its use in radio receivers.
This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The I... more This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The IC is comprised of a Sigma-Delta A/D converter and a digital AM/FM demodulator. The Sigma Delta modulator converts the standard 10.7 MHz IF signal, allowing the use of digital channel-select filtering, providing improved performance over analog filtering. Subsequent demodulation and signal processing are performed digitally, allowing flexibility in the algorithms employed and greater integration with other digital circuitry in the system. There is also a software element to the system, as the stereo decoder and RDS decoding functions are implemented by DSP off-chip rather than on dedicated hardware. Behavioural-level simulations of the system are presented, which show it meets the requirements of 80 db SNR for stereo FM input signals over a 150 kHz bandwidth.
... Charge-Pump Phase-Locked Loops Diarmuid Collins †, Aidan Keady, Grzegorz Szczepkowski &am... more ... Charge-Pump Phase-Locked Loops Diarmuid Collins †, Aidan Keady, Grzegorz Szczepkowski & Ronan Farrell Institute of Microelectronics and Wireless Systems National University of Ireland Maynooth MCCI, Tyndall National Institute, Cork, Ireland ... [14] R. Baird and T. Fiez ...
European Solid-State Circuits Conference, 1999
This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for ... more This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for conversion of the IF signal. The architecture used is efficient in terms of silicon area usage and has improved performance over previous bandpass converters, allowing the IF to be at a higher frequency than the modulator clock rate. A chopping scheme is used to shift signals from the passband to DC and a lowpass modulator running at a decimated clockrate performs the A/D conversion. Simulation results, along with test results from an IC implementation of the converter, are presented to show the operation of the circuit and its use in radio receivers.
This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The I... more This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The IC is comprised of a Sigma-Delta A/D converter and a digital AM/FM demodulator. The Sigma Delta modulator converts the standard 10.7 MHz IF signal, allowing the use of digital channel-select filtering, providing improved performance over analog filtering. Subsequent demodulation and signal processing are performed digitally, allowing flexibility in the algorithms employed and greater integration with other digital circuitry in the system. There is also a software element to the system, as the stereo decoder and RDS decoding functions are implemented by DSP off-chip rather than on dedicated hardware. Behavioural-level simulations of the system are presented, which show it meets the requirements of 80 db SNR for stereo FM input signals over a 150 kHz bandwidth
Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL outpu... more Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL output signal resulting in a static phase offset. Classical analog approaches to reducing this offset consume large silicon area and increase gate leak- age mismatch. For ultra-deep-submicron (UDSM) technologies where gate leakage in- creases dramatically, reduction of static phase offset through digital calibration becomes more favorable. This paper presents a novel technique which digitally calibrates static phase offset down to < 10 ps for a PLL operating at 4.8 GHz, designed using a 1V 90nm CMOS process. Calibration is completed in only 2 steps, making the proposed technique suitable for systems requiring frequent switching such as frequency hopping systems commonly used in today’s wireless communication systems.
This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for ... more This paper describes a bandpass Sigma-Delta A/D converter for use in digital radio receivers for conversion of the IF signal. The architecture used is efficient in terms of silicon area usage and has improved performance over previous bandpass converters, allowing the IF to be at a higher frequency than the modulator clock rate. A chopping scheme is used to shift signals from the passband to DC and a lowpass modulator running at a decimated clockrate performs the A/D conversion. Simulation results, along with test results from an IC implementation of the converter, are presented to show the operation of the circuit and its use in radio receivers.
This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The I... more This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The IC is comprised of a Sigma-Delta A/D converter and a digital AM/FM demodulator. The Sigma Delta modulator converts the standard 10.7 MHz IF signal, allowing the use of digital channel-select filtering, providing improved performance over analog filtering. Subsequent demodulation and signal processing are performed digitally, allowing flexibility in the algorithms employed and greater integration with other digital circuitry in the system. There is also a software element to the system, as the stereo decoder and RDS decoding functions are implemented by DSP off-chip rather than on dedicated hardware. Behavioural-level simulations of the system are presented, which show it meets the requirements of 80 db SNR for stereo FM input signals over a 150 kHz bandwidth.
... Charge-Pump Phase-Locked Loops Diarmuid Collins †, Aidan Keady, Grzegorz Szczepkowski &am... more ... Charge-Pump Phase-Locked Loops Diarmuid Collins †, Aidan Keady, Grzegorz Szczepkowski & Ronan Farrell Institute of Microelectronics and Wireless Systems National University of Ireland Maynooth MCCI, Tyndall National Institute, Cork, Ireland ... [14] R. Baird and T. Fiez ...