M.S. Bhat - Academia.edu (original) (raw)
Papers by M.S. Bhat
Journal of Earth System Science, Feb 2, 2023
2017 International Conference on Innovations in Electronics, Signal Processing and Communication (IESC)
Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Ox... more Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using Ino.75 Gao.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent Ion/Iqff. Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of Ino.75 Gao.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm_max ≈ 293.626 μS/μm, subthreshold slope SS ≈ 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Ensuring security through the use of video surveillance cameras at public places is becoming attr... more Ensuring security through the use of video surveillance cameras at public places is becoming attractive these days, thanks to the efficient compression, transmission and storage schemes. To up-scale the surveillance mechanism to large sensor networks, it is imperative that the applications become compatible to wireless sensor networks using Internet of Things (IoT) infrastructure. IoT nodes are generally energy and bandwidth-limited owing to their small size and large scale deployment. Therefore, any image/video acquisition application using IoT infrastructure should function within these constraints. Compressed sensing (CS) is one such paradigm that uses simultaneous sensing and compression and provides a technique for efficient image/video acquisition. This paper investigates the use of compressed sensing for image acquisition in IoT based applications that suffer from energy, bandwidth and storage limitations.
International Journal of Circuit Theory and Applications, 2020
An ultra‐low voltage, low power bulk‐driven voltage follower (VF) is proposed in this paper. Furt... more An ultra‐low voltage, low power bulk‐driven voltage follower (VF) is proposed in this paper. Further, it is exploited to design a fourth‐order low‐pass filter (LPF) for electrocardiogram (ECG) signal processing. The filter is designed in UMC 180‐nm CMOS technology and operates with an ultra‐low supply voltage of 0.3 V. It consumes an extremely low power of 2.4 nW for a cutoff frequency of 100 Hz. Results of post‐layout simulation show that the proposed filter provides a dynamic range (DR) of 51.6 dB even from a 0.3‐V supply voltage. The filter achieves a Figure‐of‐merit (FoM) of 4.7 × 10−15, which is better than many designs listed in the literature.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Clean water and electricity are the two major public utilities for any society and it is the resp... more Clean water and electricity are the two major public utilities for any society and it is the responsibility of each consumer to use these resources efficiently and minimize the wastage. This paper presents a distributed control scheme to address these issues for each utility. In this scheme, wireless sensor network is used for on-line monitoring and automated control of water in overhead tanks. In a similar way, using energy meters and intelligent circuit breakers, the power consumption is remotely monitored and power delivery is automated. A cloud based user application is developed through which authorized operators can view the complete data of water flow as well as energy consumption at desired locations on a single graphical user interface (GUI). The distributed control is developed using Internet enabled embedded boards along with sensors and supporting network nodes. IBM’s Watson IoT platform is used for data acquisition, analysis and control.
2018 8th International Symposium on Embedded Computing and System Design (ISED), 2018
This work presents low loss RF-MEMS Single Pole Four Throw (SP4T) switch for X band. The present ... more This work presents low loss RF-MEMS Single Pole Four Throw (SP4T) switch for X band. The present work is inspired from the fact that electrostatically actuated RF MEMS switches have superior RF performance over the state-of-the-art solid-state switches. Since an optimized design for Single Pole Multi Throw (SPMT) switch is difficult to realize, this work proposes a new design to achieve low loss and high isolation. The idea is to realize a combination of SPST (Single-Pole-Single-Throw) series and shunt switching in each arm of the SP4T model. The actuation voltage, isolation and insertion losses are optimized. The electro-mechanical modeling of the proposed device is done in CoventorWare and electro-magnetic modeling in HFSS. The simulation of the proposed design shows an actuation voltage of 12 V for capacitive shunt configuration and 13.75 V for the lateral series switch. The insertion loss and isolation are better than 1 dB and -50 dB respectively in the X band. The excellent RF characteristics make the switches suitable as MEMS varactors for high frequency applications and in tunable MEMS filters and phaseshifters.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction... more Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction is all the more important to derive maximum performance mileage. Retiming is a powerful sequential optimization technique used to move registers across the combinational logic or to optimize the number of registers to improve performance via power-delay trade-off, without changing the input-output behavior of the circuit. This paper presents a high-level technique to retime a given sequential circuit to achieve lower clock period and a lower register count and their trade-off. The techniques used in this paper include cutset retiming, retiming for clock period minimization and retiming for register minimization. An environment is created using MATLAB, which takes a non-retimed circuit in the form of a netlist and a retimed netlist is generated with reduced critical path and/or with reduced number of flip-flops, thereby improving the overall performance.
Journal of Low Power Electronics, 2017
International Journal of Mechatronics and Automation, 2018
Microelectromechanical systems (MEMS) capacitive switches discussed in this paper employ electros... more Microelectromechanical systems (MEMS) capacitive switches discussed in this paper employ electrostatic actuation to perform switching. Capacitive switches employ inductive tuning for excellent switching characteristics in X and Ku bands. Employing inductive tuning is found to increase the switch beam inductance by a few tens of pico-henry. This enhances the Q factor and enables tuning of isolation over a narrow band of frequencies. Beam inductance can be extracted from the simulated isolation characteristics of the switch by curve fitting. This paper presents design, fabrication and characterisation of inductive tuned MEMS capacitive switches tuned for X and Ku bands. The devices are fabricated on high resistive (10 KΩ) silicon substrate by a five mask process. The characterisation of the fabricated devices are conducted using Cascade probe station and high frequency Power network analyser. Characterisation results show an actuation voltage of 18.5 volts. The insertion-loss and isolation are better than 0.5 dB and-40 dB respectively in the 8-18 GHz band.
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2016
This paper presents a novel handheld electrochemical workstation for serum albumin measurement. T... more This paper presents a novel handheld electrochemical workstation for serum albumin measurement. The system consists of a multi-path potentiostat module which performs electrochemical measurements on disposable test strip. The strip provides a port for applying blood sample. The test strip consists of 3 electrochemical cells for redundancy and parallel testing. The 3 sets of 3 electrodes (Working, Reference and Counter electrodes) are screen printed on a Polyethylene Terephthalate (PET) substrate. The system provides the unique capability of performing Cyclic Voltammetry and Chrono Amperometry measurements in three parallel paths. The system is very generic and flexible, with user defined inputs for voltage, sweep rate and time through 5 inch capacitive touch screen. The experimental results can be stored on micro SD card and the data is accessible with USB or Bluetooth interface. This paper reports an extensive characterization of system through several tests conducted on standard redox solution. The system is then validated for human serum albumin measurement, using clinical samples. This is the first ever point of care handheld diagnostic device in the world for human serum albumin measurement.
Journal of Low Power Electronics, 2015
2014 Fifth International Symposium on Electronic System Design, 2014
This work attempts inductive tuning of Radio Frequency Micro Electro Mechanical (RF MEM) capaciti... more This work attempts inductive tuning of Radio Frequency Micro Electro Mechanical (RF MEM) capacitive switches for independent operation in X and Ku bands. The usual isolation characteristics of MEMS switches show wide bandwidth and moderate isolation of around 30 dB. Inductive tuning increases switch beam inductance by a few tens of pico henries. This enhances the Q factor and has the effect of improving the isolation and reducing the bandwidth of the switches. Inductive tuning is achieved by creating notches in the coplanar waveguide (CPW) ground plane in close proximity to the membrane. Membrane inductance enhancement can also be achieved by employing folded suspension beams. Since the current is concentrated on the edges of the signal and ground plane, the part of the beam over the CPW gap will have a dominating effect over the beam inductance. Beam inductance can be extracted from the simulated isolation characteristics of the switch by curve fitting. This paper presents tuning of two different rectangular coil suspension beam geometries to improve the isolation characteristics in the respective bands of frequencies.
International Journal of Signal and Imaging Systems Engineering, 2009
ABSTRACT In this paper, we propose models for single, coupled, L and T type on-chip global interc... more ABSTRACT In this paper, we propose models for single, coupled, L and T type on-chip global interconnect lines. Generalised models for different interconnect geometries are formed by distributed RLGC parameters using state space approach. Interconnect delay for a single interconnect line is estimated using our model and compared with other models. It is found that the error in the estimation of the delay is less in our model. Also interconnect performance metrics for the proposed models are obtained for 65 nm, 90 nm, 130nm and 180nm technology nodes based on Predictive Technology Model (PTM) values. In case of coupled, L and T section interconnects, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and can be used to characterise any interconnect structure. Further, the state matrices for any length of interconnect can be obtained by considering suitable number of rlgc segments.
International Journal of Computer and Electrical Engineering, 2012
Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integ... more Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integrity issue in integrated circuits operating at Giga-Hertz (GHz) frequencies. In this paper, we propose a method to reduce such via induced signal reflections in on-chip global interconnect lines. We show that the impedance matching can be achieved by the inclusion of an appropriate capacitive load at the junction of the on-chip interconnect line and via. Expressions to determine the capacitance value to be added at via-interconnect junction is derived. Simulation results show that the signal refection is reduced to less than-10 dB in the frequency range of 1 GHz to 10 GHz using the proposed method in 65 nm technology. Proposed method is tested for two types of models-(i) Two interconnect layers connected through a single via and (ii) Two interconnect layers connected from layer 6 to layer 1 through five vias.
2008 International Conference on Electronic Design, 2008
In this paper, we present the development of an open source tool, AutoLibGen, for characterising ... more In this paper, we present the development of an open source tool, AutoLibGen, for characterising a standard cell library comprising of basic combinational circuits. The cells are initially laid out and the parasitic netlists are extracted. Unlike the traditional method of computing timing and power data using non linear delay and power models we use more accurate composite current source (CCS) based characterization for very deep sub-micron technologies. We tested our tool with a library for 65 nm. The library file generated by our tool was successfully compiled by synopsys library compiler and is used to synthesize a Verilog code using synopsys design compiler.
IET Circuits, Devices & Systems
2019 9th International Symposium on Embedded Computing and System Design (ISED)
This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in ... more This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)
This paper proposes an ultra low voltage, low power transconductor. By using the proposed transco... more This paper proposes an ultra low voltage, low power transconductor. By using the proposed transconductor, a 4th order Butterworth low-pass filter (LPF) for the processing of an Electrocardiogram (ECG), is implemented. The filter operates from an extremely low power supply of 0.3 V. For 100 Hz cutoff frequency, the filter offers a dynamic range (DR) of 49.3 dB and consumes 2.4 nW power. The filter offers a Figure-of-merit (FoM) of 6.2 × 10-15, which is much superior to those enumerated in the literature.
Sādhanā, 2019
A compact programmable-resolution successive approximation register (SAR) analog to digital conve... more A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 lW achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm 2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 169 degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits.
IEEE Transactions on Electron Devices, 2017
Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed whil... more Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. Index Terms-Drain extended MOS (DeMOS), electrostatic discharge (ESD), hot carrier injection (HCI), safe operating area (SOA), superjunction (SJ). I. INTRODUCTION S YSTEM ON CHIP (SoC) using advanced CMOS technology nodes is high in demand for hand-held applications like tablets and cellphones [1]. An SoC concept intrinsically demands integration of low-voltage functionalities like digital core, high-voltage functionalities like input/output interfaces, RF functionalities like power amplifiers and power electronics like dc-dc converters for on-chip power management. Such an integration seriously cuts down the manufacturing cost and reduces the time to market. However, except digital cores, other functionalities require high-voltage/high-power switching or RF devices [2], [3], offered over the same technology platform for cost-efficient integration within the same chip. In CMOS technologies, conventional nonshallow trench isolation (STI) drain extended MOS (DeMOS) devices, as depicted in Fig. 1(a), are commonly used for high-voltage operation. Designing such high-voltage devices in ultrascaled
Journal of Earth System Science, Feb 2, 2023
2017 International Conference on Innovations in Electronics, Signal Processing and Communication (IESC)
Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Ox... more Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using Ino.75 Gao.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent Ion/Iqff. Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of Ino.75 Gao.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm_max ≈ 293.626 μS/μm, subthreshold slope SS ≈ 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Ensuring security through the use of video surveillance cameras at public places is becoming attr... more Ensuring security through the use of video surveillance cameras at public places is becoming attractive these days, thanks to the efficient compression, transmission and storage schemes. To up-scale the surveillance mechanism to large sensor networks, it is imperative that the applications become compatible to wireless sensor networks using Internet of Things (IoT) infrastructure. IoT nodes are generally energy and bandwidth-limited owing to their small size and large scale deployment. Therefore, any image/video acquisition application using IoT infrastructure should function within these constraints. Compressed sensing (CS) is one such paradigm that uses simultaneous sensing and compression and provides a technique for efficient image/video acquisition. This paper investigates the use of compressed sensing for image acquisition in IoT based applications that suffer from energy, bandwidth and storage limitations.
International Journal of Circuit Theory and Applications, 2020
An ultra‐low voltage, low power bulk‐driven voltage follower (VF) is proposed in this paper. Furt... more An ultra‐low voltage, low power bulk‐driven voltage follower (VF) is proposed in this paper. Further, it is exploited to design a fourth‐order low‐pass filter (LPF) for electrocardiogram (ECG) signal processing. The filter is designed in UMC 180‐nm CMOS technology and operates with an ultra‐low supply voltage of 0.3 V. It consumes an extremely low power of 2.4 nW for a cutoff frequency of 100 Hz. Results of post‐layout simulation show that the proposed filter provides a dynamic range (DR) of 51.6 dB even from a 0.3‐V supply voltage. The filter achieves a Figure‐of‐merit (FoM) of 4.7 × 10−15, which is better than many designs listed in the literature.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Clean water and electricity are the two major public utilities for any society and it is the resp... more Clean water and electricity are the two major public utilities for any society and it is the responsibility of each consumer to use these resources efficiently and minimize the wastage. This paper presents a distributed control scheme to address these issues for each utility. In this scheme, wireless sensor network is used for on-line monitoring and automated control of water in overhead tanks. In a similar way, using energy meters and intelligent circuit breakers, the power consumption is remotely monitored and power delivery is automated. A cloud based user application is developed through which authorized operators can view the complete data of water flow as well as energy consumption at desired locations on a single graphical user interface (GUI). The distributed control is developed using Internet enabled embedded boards along with sensors and supporting network nodes. IBM’s Watson IoT platform is used for data acquisition, analysis and control.
2018 8th International Symposium on Embedded Computing and System Design (ISED), 2018
This work presents low loss RF-MEMS Single Pole Four Throw (SP4T) switch for X band. The present ... more This work presents low loss RF-MEMS Single Pole Four Throw (SP4T) switch for X band. The present work is inspired from the fact that electrostatically actuated RF MEMS switches have superior RF performance over the state-of-the-art solid-state switches. Since an optimized design for Single Pole Multi Throw (SPMT) switch is difficult to realize, this work proposes a new design to achieve low loss and high isolation. The idea is to realize a combination of SPST (Single-Pole-Single-Throw) series and shunt switching in each arm of the SP4T model. The actuation voltage, isolation and insertion losses are optimized. The electro-mechanical modeling of the proposed device is done in CoventorWare and electro-magnetic modeling in HFSS. The simulation of the proposed design shows an actuation voltage of 12 V for capacitive shunt configuration and 13.75 V for the lateral series switch. The insertion loss and isolation are better than 1 dB and -50 dB respectively in the X band. The excellent RF characteristics make the switches suitable as MEMS varactors for high frequency applications and in tunable MEMS filters and phaseshifters.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2018
Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction... more Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction is all the more important to derive maximum performance mileage. Retiming is a powerful sequential optimization technique used to move registers across the combinational logic or to optimize the number of registers to improve performance via power-delay trade-off, without changing the input-output behavior of the circuit. This paper presents a high-level technique to retime a given sequential circuit to achieve lower clock period and a lower register count and their trade-off. The techniques used in this paper include cutset retiming, retiming for clock period minimization and retiming for register minimization. An environment is created using MATLAB, which takes a non-retimed circuit in the form of a netlist and a retimed netlist is generated with reduced critical path and/or with reduced number of flip-flops, thereby improving the overall performance.
Journal of Low Power Electronics, 2017
International Journal of Mechatronics and Automation, 2018
Microelectromechanical systems (MEMS) capacitive switches discussed in this paper employ electros... more Microelectromechanical systems (MEMS) capacitive switches discussed in this paper employ electrostatic actuation to perform switching. Capacitive switches employ inductive tuning for excellent switching characteristics in X and Ku bands. Employing inductive tuning is found to increase the switch beam inductance by a few tens of pico-henry. This enhances the Q factor and enables tuning of isolation over a narrow band of frequencies. Beam inductance can be extracted from the simulated isolation characteristics of the switch by curve fitting. This paper presents design, fabrication and characterisation of inductive tuned MEMS capacitive switches tuned for X and Ku bands. The devices are fabricated on high resistive (10 KΩ) silicon substrate by a five mask process. The characterisation of the fabricated devices are conducted using Cascade probe station and high frequency Power network analyser. Characterisation results show an actuation voltage of 18.5 volts. The insertion-loss and isolation are better than 0.5 dB and-40 dB respectively in the 8-18 GHz band.
2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 2016
This paper presents a novel handheld electrochemical workstation for serum albumin measurement. T... more This paper presents a novel handheld electrochemical workstation for serum albumin measurement. The system consists of a multi-path potentiostat module which performs electrochemical measurements on disposable test strip. The strip provides a port for applying blood sample. The test strip consists of 3 electrochemical cells for redundancy and parallel testing. The 3 sets of 3 electrodes (Working, Reference and Counter electrodes) are screen printed on a Polyethylene Terephthalate (PET) substrate. The system provides the unique capability of performing Cyclic Voltammetry and Chrono Amperometry measurements in three parallel paths. The system is very generic and flexible, with user defined inputs for voltage, sweep rate and time through 5 inch capacitive touch screen. The experimental results can be stored on micro SD card and the data is accessible with USB or Bluetooth interface. This paper reports an extensive characterization of system through several tests conducted on standard redox solution. The system is then validated for human serum albumin measurement, using clinical samples. This is the first ever point of care handheld diagnostic device in the world for human serum albumin measurement.
Journal of Low Power Electronics, 2015
2014 Fifth International Symposium on Electronic System Design, 2014
This work attempts inductive tuning of Radio Frequency Micro Electro Mechanical (RF MEM) capaciti... more This work attempts inductive tuning of Radio Frequency Micro Electro Mechanical (RF MEM) capacitive switches for independent operation in X and Ku bands. The usual isolation characteristics of MEMS switches show wide bandwidth and moderate isolation of around 30 dB. Inductive tuning increases switch beam inductance by a few tens of pico henries. This enhances the Q factor and has the effect of improving the isolation and reducing the bandwidth of the switches. Inductive tuning is achieved by creating notches in the coplanar waveguide (CPW) ground plane in close proximity to the membrane. Membrane inductance enhancement can also be achieved by employing folded suspension beams. Since the current is concentrated on the edges of the signal and ground plane, the part of the beam over the CPW gap will have a dominating effect over the beam inductance. Beam inductance can be extracted from the simulated isolation characteristics of the switch by curve fitting. This paper presents tuning of two different rectangular coil suspension beam geometries to improve the isolation characteristics in the respective bands of frequencies.
International Journal of Signal and Imaging Systems Engineering, 2009
ABSTRACT In this paper, we propose models for single, coupled, L and T type on-chip global interc... more ABSTRACT In this paper, we propose models for single, coupled, L and T type on-chip global interconnect lines. Generalised models for different interconnect geometries are formed by distributed RLGC parameters using state space approach. Interconnect delay for a single interconnect line is estimated using our model and compared with other models. It is found that the error in the estimation of the delay is less in our model. Also interconnect performance metrics for the proposed models are obtained for 65 nm, 90 nm, 130nm and 180nm technology nodes based on Predictive Technology Model (PTM) values. In case of coupled, L and T section interconnects, the effect of mutual inductance and coupling capacitance is considered in addition to the distributed RLGC parameters. The proposed models are generic in nature and can be used to characterise any interconnect structure. Further, the state matrices for any length of interconnect can be obtained by considering suitable number of rlgc segments.
International Journal of Computer and Electrical Engineering, 2012
Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integ... more Signal reflections due to impedance mismatch at via-interconnect junction is a major signal integrity issue in integrated circuits operating at Giga-Hertz (GHz) frequencies. In this paper, we propose a method to reduce such via induced signal reflections in on-chip global interconnect lines. We show that the impedance matching can be achieved by the inclusion of an appropriate capacitive load at the junction of the on-chip interconnect line and via. Expressions to determine the capacitance value to be added at via-interconnect junction is derived. Simulation results show that the signal refection is reduced to less than-10 dB in the frequency range of 1 GHz to 10 GHz using the proposed method in 65 nm technology. Proposed method is tested for two types of models-(i) Two interconnect layers connected through a single via and (ii) Two interconnect layers connected from layer 6 to layer 1 through five vias.
2008 International Conference on Electronic Design, 2008
In this paper, we present the development of an open source tool, AutoLibGen, for characterising ... more In this paper, we present the development of an open source tool, AutoLibGen, for characterising a standard cell library comprising of basic combinational circuits. The cells are initially laid out and the parasitic netlists are extracted. Unlike the traditional method of computing timing and power data using non linear delay and power models we use more accurate composite current source (CCS) based characterization for very deep sub-micron technologies. We tested our tool with a library for 65 nm. The library file generated by our tool was successfully compiled by synopsys library compiler and is used to synthesize a Verilog code using synopsys design compiler.
IET Circuits, Devices & Systems
2019 9th International Symposium on Embedded Computing and System Design (ISED)
This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in ... more This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V.
2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)
This paper proposes an ultra low voltage, low power transconductor. By using the proposed transco... more This paper proposes an ultra low voltage, low power transconductor. By using the proposed transconductor, a 4th order Butterworth low-pass filter (LPF) for the processing of an Electrocardiogram (ECG), is implemented. The filter operates from an extremely low power supply of 0.3 V. For 100 Hz cutoff frequency, the filter offers a dynamic range (DR) of 49.3 dB and consumes 2.4 nW power. The filter offers a Figure-of-merit (FoM) of 6.2 × 10-15, which is much superior to those enumerated in the literature.
Sādhanā, 2019
A compact programmable-resolution successive approximation register (SAR) analog to digital conve... more A compact programmable-resolution successive approximation register (SAR) analog to digital converter (ADC) for biosignal acquisition system is presented. The ADC features a programmable 4-to-8-bit DAC that makes the ADC programmable with 2 bits evaluated in each clock cycle. At low resolution with relaxed noise and linearity requirements, use of an increased clock speed improves energy efficiency. A single DAC architecture is used to generate references for 2 bits per cycle evaluation for all resolutions. Nonbinary switched capacitor circuits, least sensitive to parasitics, are proposed for the use in DAC for reference generation. The choice of architecture and circuit design are presented with mathematical analysis. The post-layout simulation of designed ADC in 90 nm CMOS process has 1.2 MS/s sampling rate at 8-bit mode with a power consumption of 185 lW achieving an ENOB of 7.6. The active area of designed ADC is 0.06 mm 2. The DAC resolution scaling and the use of variable sampling rate maximize efficiency at lower resolutions. Therefore, figure of merit (FOM) is degraded only by a factor of 4.7 for resolution scaling from 8 to 4 bits. This is a significant improvement over 169 degradation expected from 8-bit to 4-bit resolution scaling by truncating the bits.
IEEE Transactions on Electron Devices, 2017
Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed whil... more Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. Index Terms-Drain extended MOS (DeMOS), electrostatic discharge (ESD), hot carrier injection (HCI), safe operating area (SOA), superjunction (SJ). I. INTRODUCTION S YSTEM ON CHIP (SoC) using advanced CMOS technology nodes is high in demand for hand-held applications like tablets and cellphones [1]. An SoC concept intrinsically demands integration of low-voltage functionalities like digital core, high-voltage functionalities like input/output interfaces, RF functionalities like power amplifiers and power electronics like dc-dc converters for on-chip power management. Such an integration seriously cuts down the manufacturing cost and reduces the time to market. However, except digital cores, other functionalities require high-voltage/high-power switching or RF devices [2], [3], offered over the same technology platform for cost-efficient integration within the same chip. In CMOS technologies, conventional nonshallow trench isolation (STI) drain extended MOS (DeMOS) devices, as depicted in Fig. 1(a), are commonly used for high-voltage operation. Designing such high-voltage devices in ultrascaled