C. Tretz - Academia.edu (original) (raw)
Papers by C. Tretz
Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996
2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000
... Niraj Subba, Akram Salman, Souvick Mitra, Dimitris E. loannou and Christophe Tretz&am... more ... Niraj Subba, Akram Salman, Souvick Mitra, Dimitris E. loannou and Christophe Tretz' ... A pseudo-nMOS gate with a fan-in of N requires only N+l transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each ...
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 1993
The modelling and design of a six-port CMOS static RAM are described. Due to minimum area constra... more The modelling and design of a six-port CMOS static RAM are described. Due to minimum area constraints imposed by the wiring matrix necessary for addressing, local interconnect, etc. the cell is relatively large; but, as a result, the cell can swing the bit line extremely quickly. The memory system, which is a true multi-port memory system, can be read and written to independently and simultaneously, subject to consistency constraints. A detailed circuit analysis and SPICE circuit simulations of the circuit extracted from a custom layout are presented
1997 IEEE International SOI Conference Proceedings, 1997
SOI has recently emerged as a serious contender for low-power high-performance applications. This... more SOI has recently emerged as a serious contender for low-power high-performance applications. This paper examines the metastability of CMOS latches based on partially-depleted (PD) SOI devices with various body-connection topologies
Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996
Most existing differential CMOS logic circuits, including ones based on pass logic, are carefully... more Most existing differential CMOS logic circuits, including ones based on pass logic, are carefully classified by topology. The breakdown of design into distinct decisions allows more meaningful performance comparisons. A study based on local comparison of the energy-delay product of basic logic functions implemented with various static differential logic families is provided as an example. Various extensions are discussed, such
Proceedings of the Sixth Great Lakes Symposium on VLSI, 1996
In this paper, we revisit three of the well known optimization results in CMOS transistor sizing ... more In this paper, we revisit three of the well known optimization results in CMOS transistor sizing with the energy-delay product as a new metric. We study the absolute sizes of and the ratio between n-channel and p-channel transistor widths in uniform logic, the optimal distance between repeaters in an RC line, and the optimum number of inverter stages, along with
International Semiconductor Device Research Symposium, 2003, 2003
ABSTRACT This paper investigates the possibility of using SDG (symmetric double gate) device intr... more ABSTRACT This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n+-poly gate and a 500 MHz on the p+-poly gate are also studied.
1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199), 1998
This paper examines the performance of differential static CMOS circuit topologies based on parti... more This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have Leff=0.15 μm. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453), 1999
In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) par... more In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999
A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, ... more A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100 nm
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004
2006 IEEE international SOI Conferencee Proceedings, 2006
The impacts of corner rounding in TG MOSFETs on DIBL and device characteristics were analyzed via... more The impacts of corner rounding in TG MOSFETs on DIBL and device characteristics were analyzed via 3D numerical simulations. Properly rounded corners of TG device can improve SCEs or increase drive current. Semi-cylindrical gate structure is preferable for heavily-doped devices, while rectangular gate structure appears better for lightly-doped devices, respectively
2005 IEEE International SOI Conference Proceedings, 2005
ABSTRACT
2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03), 2003
Solid-State Electronics, 2004
In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for lo... more In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for low voltage/low power circuits. The logic gates are based on ratioed logic with depletion-mode (i.e., intrinsically on) Symmetric DG (SDG) load transistors and inversion-mode Asymmetric DG (ADG) driver transistors. Using this technique a basic inverter was designed, with better performance compared to ''classical'' CMOS DG design. This technique was extended to create a complete set of basic logic gates including NOR2, NAND2 and XOR2 gates.
International Journal of Electronics, 1999
IEEE Transactions on Electron Devices, 2005
Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND... more Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front-and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.
IEEE Transactions on Electron Devices, 2000
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG... more Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (V T ) difference between double-gated and single-gated modes in a high-V T DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations.
Charge pump circuits are used to produce voltages higher than the regular supply voltage on chip.... more Charge pump circuits are used to produce voltages higher than the regular supply voltage on chip. They are essential for single-power nonvolatile memories such as EEPROMS and Flash memories. However, the pumping gain and efficiency for bulk circuits are severely ...
Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996
2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125), 2000
... Niraj Subba, Akram Salman, Souvick Mitra, Dimitris E. loannou and Christophe Tretz&am... more ... Niraj Subba, Akram Salman, Souvick Mitra, Dimitris E. loannou and Christophe Tretz' ... A pseudo-nMOS gate with a fan-in of N requires only N+l transistors (as opposed to 2N for standard CMOS), resulting in smaller area as well as smaller parasitic capacitances, whereas each ...
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93, 1993
The modelling and design of a six-port CMOS static RAM are described. Due to minimum area constra... more The modelling and design of a six-port CMOS static RAM are described. Due to minimum area constraints imposed by the wiring matrix necessary for addressing, local interconnect, etc. the cell is relatively large; but, as a result, the cell can swing the bit line extremely quickly. The memory system, which is a true multi-port memory system, can be read and written to independently and simultaneously, subject to consistency constraints. A detailed circuit analysis and SPICE circuit simulations of the circuit extracted from a custom layout are presented
1997 IEEE International SOI Conference Proceedings, 1997
SOI has recently emerged as a serious contender for low-power high-performance applications. This... more SOI has recently emerged as a serious contender for low-power high-performance applications. This paper examines the metastability of CMOS latches based on partially-depleted (PD) SOI devices with various body-connection topologies
Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1996
Most existing differential CMOS logic circuits, including ones based on pass logic, are carefully... more Most existing differential CMOS logic circuits, including ones based on pass logic, are carefully classified by topology. The breakdown of design into distinct decisions allows more meaningful performance comparisons. A study based on local comparison of the energy-delay product of basic logic functions implemented with various static differential logic families is provided as an example. Various extensions are discussed, such
Proceedings of the Sixth Great Lakes Symposium on VLSI, 1996
In this paper, we revisit three of the well known optimization results in CMOS transistor sizing ... more In this paper, we revisit three of the well known optimization results in CMOS transistor sizing with the energy-delay product as a new metric. We study the absolute sizes of and the ratio between n-channel and p-channel transistor widths in uniform logic, the optimal distance between repeaters in an RC line, and the optimum number of inverter stages, along with
International Semiconductor Device Research Symposium, 2003, 2003
ABSTRACT This paper investigates the possibility of using SDG (symmetric double gate) device intr... more ABSTRACT This paper investigates the possibility of using SDG (symmetric double gate) device intrinsically on structure as a load device for DG-SOI based ratioed logic, To establish the feasibility and superiority of this approach an inverter and a NOR gate were designed, which exhibits considerable advantages. The work is then extented to show how the approach can also be used to built NAND and XOR gates to create a complete logic family. All the simulations are done for 50 nm gate length devices using SILVACO tools. Voltage transfer characteristics are studied for both SDG load and ADG (asymmetric double gate) inverter. The transient characteristics obtained with a 1.25 GHz pulse on the n+-poly gate and a 500 MHz on the p+-poly gate are also studied.
1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199), 1998
This paper examines the performance of differential static CMOS circuit topologies based on parti... more This paper examines the performance of differential static CMOS circuit topologies based on partially-depleted (PD) and dual-gate SOI devices. Both device types have Leff=0.15 μm. The top and bottom gates of the dual-gate device are self-aligned to the source/drain, and the device has a fanned-out source/drain structure with low parasitic resistance. The dual-gate device current drive and transconductance are about
1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453), 1999
In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) par... more In this paper the hysteretic (history-dependent) propagation gate delay of floating-body (FB) partially depleted (PD) SOI CMOS circuits is investigated. The change in gate propagation delay with time is examined with no preconditioning of the floating-body. The simulation-based analysis includes the sensitivity of the hysteresis to supply voltage, Wp/Wn (beta ratio), duty cycle, slew rate, output load, and initial state
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), 1999
A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, ... more A new methodology to characterize and analyze hysteresis in PD/SOI CMOS inverter-based circuits, including its true worst case, is defined, and new insight into the underlying physics is provided. The methodology is used to explore novel device/circuit designs for controlling hysteresis as the PD/SOI CMOS technology is scaled to <100 nm
2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573), 2004
2006 IEEE international SOI Conferencee Proceedings, 2006
The impacts of corner rounding in TG MOSFETs on DIBL and device characteristics were analyzed via... more The impacts of corner rounding in TG MOSFETs on DIBL and device characteristics were analyzed via 3D numerical simulations. Properly rounded corners of TG device can improve SCEs or increase drive current. Semi-cylindrical gate structure is preferable for heavily-doped devices, while rectangular gate structure appears better for lightly-doped devices, respectively
2005 IEEE International SOI Conference Proceedings, 2005
ABSTRACT
2003 IEEE International Conference on Robotics and Automation (Cat No 03CH37422) SOI-03), 2003
Solid-State Electronics, 2004
In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for lo... more In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for low voltage/low power circuits. The logic gates are based on ratioed logic with depletion-mode (i.e., intrinsically on) Symmetric DG (SDG) load transistors and inversion-mode Asymmetric DG (ADG) driver transistors. Using this technique a basic inverter was designed, with better performance compared to ''classical'' CMOS DG design. This technique was extended to create a complete set of basic logic gates including NOR2, NAND2 and XOR2 gates.
International Journal of Electronics, 1999
IEEE Transactions on Electron Devices, 2005
Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND... more Novel high-density low-power double-gate circuit techniques for basic logic families such as NAND, NOR, and pass-gate are proposed. The technique exploits the independent front-and back-gate bias to reduce the number of transistors for implementing logic functions. The scheme substantially improves the standby and dynamic power consumptions by reducing the number of transistors and the chip area/size while improving the circuit performance. The power/performance advantages are analyzed/validated via mixed-mode two-dimensional MEDICI numerical device simulations, as well as by using physical delay equations.
IEEE Transactions on Electron Devices, 2000
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG... more Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (V T ) difference between double-gated and single-gated modes in a high-V T DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations.
Charge pump circuits are used to produce voltages higher than the regular supply voltage on chip.... more Charge pump circuits are used to produce voltages higher than the regular supply voltage on chip. They are essential for single-power nonvolatile memories such as EEPROMS and Flash memories. However, the pumping gain and efficiency for bulk circuits are severely ...