Daihyun Lim - Academia.edu (original) (raw)

Papers by Daihyun Lim

Vlsic, 2004

This paper describes a technique that exploits the statistical delay variations of wires and tran... more This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing the proposed circuit to identify individual ICs. Further, the circuit functions reliably over a practical range of environmental variation such as temperature and voltage.

Abstract—Modern cryptographic protocols are based on the premise that only authorized participant... more Abstract—Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such ...

Proceedings of the 9th ACM conference on Computer and communications security - CCS '02, 2002

Page 1. Silicon Physical Random Functions∗ Blaise Gassend, Dwaine Clarke, Marten van Dijk† and Sr... more Page 1. Silicon Physical Random Functions∗ Blaise Gassend, Dwaine Clarke, Marten van Dijk† and Srinivas ... declarke,marten,devadas}@mit.edu ABSTRACT We introduce the notion of a Physical Random Function (PUF). We argue that a ...

... |z11 | 50 60 70 80 90 100 101 102 Frequency (GHz) |z11 | ) mW1 log( 10 10 FTR log 20 PN FOM 0... more ... |z11 | 50 60 70 80 90 100 101 102 Frequency (GHz) |z11 | ) mW1 log( 10 10 FTR log 20 PN FOM 0 T DISS P f f Phase Noise Measurement with an on-chip divider Ś VCO phase noise = -106.14dBc/Hz @10MHz offset Ś FOM = -175.8dBc/Hz Ś FOMT = -175.4dBc/Hz ...

Noise in Devices and Circuits III, 2005

While pseudo random number generators based on computational complexity are widely used for most ... more While pseudo random number generators based on computational complexity are widely used for most of cryptographic applications and probabilistic simulations, the generation of true random numbers based on physical randomness is required to guarantee the advanced security of cryptographic systems. In this paper we present a method to exploit manufacturing variations, metastablity, and thermal noise in integrated circuits to generate random numbers. This metastability based physical random number generator provides a compact and low-power solution which can be fabricated using standard IC manufacturing processes. Test-chips were fabricated in TSMC 0.18um process and experimental results show that the generated random bits pass standard randomness tests successfully. The operation of the proposed scheme is robust against environmental changes since it can be re-calibrated to new environmental conditions such as temperature and power supply voltage.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004

This paper describes a technique that exploits the statistical delay variations of wires and tran... more This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing the proposed circuit to identify individual ICs. Further, the circuit functions reliably over a practical range of environmental variation such as temperature and voltage.

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

... The oscillation fre-Choongyeun Cho', Weipeng Li3... more ... The oscillation fre-Choongyeun Cho', Weipeng Li3, Daihyun Lim4, Robert Trzcinski, quency of the same circuit with VCTRL sweep is shown in the right Mahender Kumar', Christine Norris', David Ahigren' plot. ... sary for the manufacturing of MMW VCO in SoC. ...

Smart Structures, Devices, and Systems II, 2005

A hardware random number generator is different from a pseudo-random number generator; a pseudo-r... more A hardware random number generator is different from a pseudo-random number generator; a pseudo-random number generator approximates the assumed behavior of a real hardware random number generator. Simple pseudo random number generators suffices for most applications, however for demanding situations such as the generation of cryptographic keys, requires an efficient and a cost effective source of random numbers. Arbiter-based Physical

2008 IEEE Compound Semiconductor Integrated Circuits Symposium, 2008

A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design co... more A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.4fJ power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

2007 IEEE Symposium on VLSI Circuits, 2007

The VCO output is handed over to the divider through a cascode A 75GHz PLL front-end, composed of... more The VCO output is handed over to the divider through a cascode A 75GHz PLL front-end, composed of complementary LC VCO, common source 12dB gain amplifier with a IOOQ polysilicon a buffer with AC coupling, and a static CML latch divider, is resistor for voltage translation, amplification, and isolation. The integrated in 65nm SOI CMOS technology. The circuitry is buffer output is AC coupled to the divider with a back-end-of line developed with milli-meter wave link specifications, technology VNCAP, depicted in . The VNCAP enables separate DC consideration, process variation, and topology selections. The PLL biasing of divider tail currents. The VNCAP area is 0l,m by 10,m front-end achieves 5.9% tuning range centered at 73.4GHz and free-has low insertion loss. Three minimum width (lx) layers (M2-M4) running phase noise of-llOdBc/Hz at 1OMHz offset with 71mW. and four double width (2x) layers (M5-M8) of are used with via

Vlsic, 2004

This paper describes a technique that exploits the statistical delay variations of wires and tran... more This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing the proposed circuit to identify individual ICs. Further, the circuit functions reliably over a practical range of environmental variation such as temperature and voltage.

Abstract—Modern cryptographic protocols are based on the premise that only authorized participant... more Abstract—Modern cryptographic protocols are based on the premise that only authorized participants can obtain secret keys and access to information systems. However, various kinds of tampering methods have been devised to extract secret keys from conditional access systems such ...

Proceedings of the 9th ACM conference on Computer and communications security - CCS '02, 2002

Page 1. Silicon Physical Random Functions∗ Blaise Gassend, Dwaine Clarke, Marten van Dijk† and Sr... more Page 1. Silicon Physical Random Functions∗ Blaise Gassend, Dwaine Clarke, Marten van Dijk† and Srinivas ... declarke,marten,devadas}@mit.edu ABSTRACT We introduce the notion of a Physical Random Function (PUF). We argue that a ...

... |z11 | 50 60 70 80 90 100 101 102 Frequency (GHz) |z11 | ) mW1 log( 10 10 FTR log 20 PN FOM 0... more ... |z11 | 50 60 70 80 90 100 101 102 Frequency (GHz) |z11 | ) mW1 log( 10 10 FTR log 20 PN FOM 0 T DISS P f f Phase Noise Measurement with an on-chip divider Ś VCO phase noise = -106.14dBc/Hz @10MHz offset Ś FOM = -175.8dBc/Hz Ś FOMT = -175.4dBc/Hz ...

Noise in Devices and Circuits III, 2005

While pseudo random number generators based on computational complexity are widely used for most ... more While pseudo random number generators based on computational complexity are widely used for most of cryptographic applications and probabilistic simulations, the generation of true random numbers based on physical randomness is required to guarantee the advanced security of cryptographic systems. In this paper we present a method to exploit manufacturing variations, metastablity, and thermal noise in integrated circuits to generate random numbers. This metastability based physical random number generator provides a compact and low-power solution which can be fabricated using standard IC manufacturing processes. Test-chips were fabricated in TSMC 0.18um process and experimental results show that the generated random bits pass standard randomness tests successfully. The operation of the proposed scheme is robust against environmental changes since it can be re-calibrated to new environmental conditions such as temperature and power supply voltage.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004

This paper describes a technique that exploits the statistical delay variations of wires and tran... more This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing the proposed circuit to identify individual ICs. Further, the circuit functions reliably over a practical range of environmental variation such as temperature and voltage.

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

... The oscillation fre-Choongyeun Cho', Weipeng Li3... more ... The oscillation fre-Choongyeun Cho', Weipeng Li3, Daihyun Lim4, Robert Trzcinski, quency of the same circuit with VCTRL sweep is shown in the right Mahender Kumar', Christine Norris', David Ahigren' plot. ... sary for the manufacturing of MMW VCO in SoC. ...

Smart Structures, Devices, and Systems II, 2005

A hardware random number generator is different from a pseudo-random number generator; a pseudo-r... more A hardware random number generator is different from a pseudo-random number generator; a pseudo-random number generator approximates the assumed behavior of a real hardware random number generator. Simple pseudo random number generators suffices for most applications, however for demanding situations such as the generation of cryptographic keys, requires an efficient and a cost effective source of random numbers. Arbiter-based Physical

2008 IEEE Compound Semiconductor Integrated Circuits Symposium, 2008

A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design co... more A 5-stage CML prescaler operating up to 84GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.4fJ power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

2007 IEEE Symposium on VLSI Circuits, 2007

The VCO output is handed over to the divider through a cascode A 75GHz PLL front-end, composed of... more The VCO output is handed over to the divider through a cascode A 75GHz PLL front-end, composed of complementary LC VCO, common source 12dB gain amplifier with a IOOQ polysilicon a buffer with AC coupling, and a static CML latch divider, is resistor for voltage translation, amplification, and isolation. The integrated in 65nm SOI CMOS technology. The circuitry is buffer output is AC coupled to the divider with a back-end-of line developed with milli-meter wave link specifications, technology VNCAP, depicted in . The VNCAP enables separate DC consideration, process variation, and topology selections. The PLL biasing of divider tail currents. The VNCAP area is 0l,m by 10,m front-end achieves 5.9% tuning range centered at 73.4GHz and free-has low insertion loss. Three minimum width (lx) layers (M2-M4) running phase noise of-llOdBc/Hz at 1OMHz offset with 71mW. and four double width (2x) layers (M5-M8) of are used with via