Khemraj Deshmukh - Academia.edu (original) (raw)

Papers by Khemraj Deshmukh

Micromachines

3D bioprinting has emerged as a tool for developing in vitro tissue models for studying disease p... more 3D bioprinting has emerged as a tool for developing in vitro tissue models for studying disease progression and drug development. The objective of the current study was to evaluate the influence of flow driven shear stress on the viability of cultured cells inside the luminal wall of a serpentine network. Fluid–structure interaction was modeled using COMSOL Multiphysics for representing the elasticity of the serpentine wall. Experimental analysis of the serpentine model was performed on the basis of a desirable inlet flow boundary condition for which the most homogeneously distributed wall shear stress had been obtained from numerical study. A blend of Gelatin-methacryloyl (GelMA) and PEGDA200 PhotoInk was used as a bioink for printing the serpentine network, while facilitating cell growth within the pores of the gelatin substrate. Human umbilical vein endothelial cells were seeded into the channels of the network to simulate the blood vessels. A Live-Dead assay was performed over a...

Neurocognitive Perspectives of Prosocial and Positive Emotional Behaviours, 2021

Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of... more Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of the same kinds of problems. This optimization technique does not suffer, however, from some of GA's difficulties; interaction in the group enhances rather than detracts from progress toward the solution. Further, a particle swarm system has memory, which the genetic algorithm does not have. In particle swarm optimization, individuals who fly past optima are tugged to return toward them; knowledge of good solutions is retained by all particles. The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm te...

Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of... more Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of the same kinds of problems. This optimization technique does not suffer, however, from some of GA's difficulties; interaction in the group enhances rather than detracts from progress toward the solution. Further, a particle swarm system has memory, which the genetic algorithm does not have. In particle swarm optimization, individuals who fly past optima are tugged to return toward them; knowledge of good solutions is retained by all particles. The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm te...

Object tracking finds many practical applications ranging from robotics, surveillance, augmented ... more Object tracking finds many practical applications ranging from robotics, surveillance, augmented reality to human-computer computer interaction, the state state-of-the- art is still far from achieving results comparable to human performance. The goal of this article is to review the state-of-the-art art tracking methods. Object tracking remains a challenging problem due to appearance change caused by pose, illumination, occlusion, and motion, among others. An effective appearance model is of prime importance for the success of a tracking algorithm that has been attracting much attention in recent years. In this survey, we empirically demonstrate the performance of the algorithm against various common failure modes in the generic object tracking problem.

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy, 2014

Full adders are exigent components in applications such as digital signal processors (DSP) archit... more Full adders are exigent components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a new 11-transistor FA .We have done HSPICE simulation runs the new design 11-T full adders .In CMOS integrated circuit design there is a tradeoff between static power consumption and technology scaling. Static power dissipation is a challenge for the circuit designer. So we reduce the static power dissipation. In order to achieve lower static power consumption, one has to scarifies design area and circuit performance. In this paper we propose a new circuit of 11-Transistor full adder in CMOS VLSI circuit

Digital Signal Processing, 2016

The structure of the ECG signal is time varying which is the supreme common source used for the p... more The structure of the ECG signal is time varying which is the supreme common source used for the purpose of diagnosis & observation and analysis of various types of diseases related to the heart in the patient. ECG recording is the process done by placing the electrodes in the specified positions at body of humans. During the process of recording, a noise distracted signal is applied to ECG signal and the ECG signal is also full of artifacts which always degrades the quality of it and establishes threats in the recording the absolute ECG signal. The artifacts mostly noticed are Power line Interference, Baseline Wander and muscle tremors. Therefore, for accuracy in the characteristics points of ECG, an ECG having good quality is essential. Generally, we notice that these kinds of noises are very common in the process and detection is needed. We found that FIR-IIR filter is giving suitability to increase the quality of it. So, here we are presenting an implementation of the FIR-IIR fil...

Flow Dynamics and Tissue Engineering of Blood Vessels, 2020

Today’s testing of VLSI chips are very much complex day by day due to increasing advancement of n... more Today’s testing of VLSI chips are very much complex day by day due to increasing advancement of nano technology. So both front-end and back-end engineers are trying to evolve a system with full testability keeping in mind the possibility of reduced product failures and missed market opportunities. BIST is a testing technique that allows a system to test automatically itself. In this paper, the simulation result performance achieved by BIST enabled UART architecture through VHDL programming is shown. The BIST used here have two modes actually i.e. test mode and UART mode .This technique generate random test pattern automatically, so it can provide less test time compared to an externally applied test pattern and helps to achieve much more productivity at the end.

Programmable Device Circuits and Systems, 2017

A continuous increase in number of transistors and operating frequency causes high power dissipat... more A continuous increase in number of transistors and operating frequency causes high power dissipation. The most important task to minimize the power is optimization of power at the logic level. This paper presents a novel power efficient pulse triggered flip-flop. Proposed flip-flop use Exclusive-or gate based clock gating scheme that reduce the power dissipation by disabling the clock signal in inactive portion of chip. In this paper replica path delay pulse generator is used to simplify the design effort. This paper presents a comparison of existing flip-flop in term of power dissipation for different input patterns. The operation of flip-flop is analyzed and is simulated using Tanner EDA in 32nm technology at room temperature in schematic level. Simulation result shows the sensible power dissipation reduction.

The genetic algorithm works with the concept of chromosomes having gene where each gene act as a ... more The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm technique which is apparently based on the flock of birds moving to the target. This effectively overcome the shortcomings of GA and provides better fitness solutions to implement in the circuit.

Object tracking has been a very active research topic in the last few years due to its growing im... more Object tracking has been a very active research topic in the last few years due to its growing importance in various applications. Performance of object tracking can be reduces due to factors such as pose variation, illumination change, occlusion, and motion blur. Existing online algorithms often encounter problems such as drift and lack of data for learning. In this paper we presented an efficient online tracking algorithm with an appearance model based on multi scale image feature space with data independent basis. Proposed appearance model do not change the feature of object in iteration. Compound order samples of both background and foreground has been taken. These samples are reduced in size using sparse measurement matrix. Classification and updating of these samples is done in compressed domain. A MATLAB code has been implemented as per the proposed method and it gives us good result of tracking in simple and difficult sequences. Keywords—Compound Order Learning, Online Track...

Programmable Device Circuits and Systems, 2017

In past low power design techniques were not primary constraint because device density and operat... more In past low power design techniques were not primary constraint because device density and operating frequency were low. Nowadays because of very large scale integration, millions of transistors are fabricated on a single chip and requirement of high performance, portable, battery based devices causes need of low power design techniques. Digital circuits are two types: combinational circuit and sequential circuit. Sequential circuit mainly consists of flip-flops. Flip-flop is basic storage element and consume large amount of power because they are clocked with system operating frequency. Clock system consists of clock distribution network and flip-flops are most power consuming subsystems. Because of continuous increase in chip complexity and operating frequency reduction of power is long-winded task. After studying various journals and conferences, in this paper various low power Flip-flop design techniques are presented.

Programmable Device Circuits and Systems, 2017

This paper describes a low-power and lower-delay SRAM (Static Random- Access Memory) Cell using p... more This paper describes a low-power and lower-delay SRAM (Static Random- Access Memory) Cell using pulsed latch circuit. The delay and power consumption of conventional SRAM Cell is reduced by replacing two NMOS access transistors with pulsed latch circuit. The main aim of the pulsed latch circuit is to reduce delay and increase the speed of the design. As, SRAM Cell is one of the basic building element of VLSI design and due to its huge demand in VLSI chips, it is necessary to reduce power and delay so as to increases the speed of the SRAM Cell. In this paper 1bit, 4bit and 8bit SRAM Cell are designed with pulsed latch circuit and their performance is compared with conventional SRAM Cell design. The conventional SRAM and proposed SRAM Cell, both designs are implemented in 32nm CMOS technology with Vdd = 1.0V in Tanner tool v16.0. In comparision with conventional SRAM Cell the proposed SRAM Cell is much better in terms of power, speed and performance. In the proposed SRAM Cell design d...

Programmable Device Circuits and Systems, 2016

This paper presents a LNA for UWB radio receiver at 2 to 6GHz victimization 0.09µm TSMC Technolog... more This paper presents a LNA for UWB radio receiver at 2 to 6GHz victimization 0.09µm TSMC Technology wherever 009µm technology is for lower power consumption. UWB radio that created up in between the frequency vary of 2GHz to 6GHz.The basic design of LNA includes a RF electronic equipment within the middle of input matching network and also the output matching network. We’ve designed a LNA that consist low noise figure, good input and output resistivity matching and high gain and stability LNA, wherever operative temperature is 27 oC gain is 20dB and would have smart stability. we have a tendency to used ltspice tool for the simplest performance and accuracy for results, this work represents associate LNA schematic compose of Common source LNA and Cascode LNA, wherever Common source LNA is employed for glorious input and output matching and also the cascode LNA for low Noise figure and high gain, an extra feature is that single terminated LNA employs inductive supply degeneration conc...

Artificial Intelligent Systems and Machine Learning, 2016

In this paper we work on the control of total power consumption of a low noise amplifier using un... more In this paper we work on the control of total power consumption of a low noise amplifier using unique design of CMOS active inductor (on chip) for the low voltage RF circuit. We tried to address a replacement methodology of passive inductors by Active Inductors (AI) to improve the circuit performance. And improved parameter like power potency, Noise Figure (NF) and alternate methodology of input and output matching of 50 ohm. Exploiting the new biasing metric, and new design methodology of 1.8v supply, leads to 5.4mW total DC power consumption. We uses 180nm CMOS technology, frequency range of 2-6GHz. This simulation offers the thought of the longer term analysis to design higher LNA in terms of low power consumption, stability and higher range of frequency of operation.

Object tracking finds many practical applications r anging from robotics, surveillance, augmented... more Object tracking finds many practical applications r anging from robotics, surveillance, augmented reali ty to computer interaction, the state -of-the- art is still far from achieving results comparable to human performance. The goal of this article is t o review the state-of-the- art tracking methods. Object tracking remains a challenging problem due to appearance change caused by pose, illumination, occlusion, and motion, amon g others. An effective appearance model is of prime importance for the success o f a tracking algorithm that has been attracting much attention in recent years. In this survey, we empirically demonstrate the performance of the algorithm against various common failure modes in t he generic object tracking problem.

International Journal of Emerging Trends in Science and Technology, May 27, 2014

Network on Chip (NoC) is a new paradigm for making interconnections within System on Chip (SoC) s... more Network on Chip (NoC) is a new paradigm for making interconnections within System on Chip (SoC) system. With the increasing chip integration and decreasing feature size the SoC does not meet the challenges of the new process technologies .The challenges include complexity and increased delay in communication and also the bus contention and arbitration slows down the data movement which degrades the overall performance of Soc. Noc is a design platform that can meet these challenges to a great extend. In the network design of the NoC the most essential things are a network topology and a routing algorithm. Routers route the packets based on the algorithm that they use. In this paper a study of the different routing algorithms for network on chip is presented that can cope up with above mentioned problems arising in SoC. The routing algorithm of a given NoC system is measured with respect to performance metrics such as latency, throughput and load distribution. Here we are about to deal with the different topologies ,switching techniques ,performance analysis of NoC routing algorithms such as XY routing algorithm, OE routing algorithm and DyAD routing algorithm . keywords- NoC , Routers, routing algorithms, latency, throughput, XY ,OE , DyAD

Springer Proceedings in Physics, 2015

Network on Chip (NoC) is an on-chip communication technology in which a large number of processin... more Network on Chip (NoC) is an on-chip communication technology in which a large number of processing elements and storage blocks are integrated on a single chip. Due to scalability, adaptive nature, well resource utilization NoCs have become popular in and has efficiently replaced SoCs. NoCs performance depends mainly on the type of routing algorithm chosen. In this paper three different types of routing algorithms are being compared firstly one is deterministic routing (XY routing algorithm), secondly three partially adaptive routing (West-first, North-last and Negative-first) and two adaptive routing (DyAD, OE) are being compared with respect to Packet Injection Rate (PIR) of load for random traffic pattern for 4 × 4 mesh topology. All these comparison and simulation is done in NOXIM 2.3.1 simulator which is a cycle accurate systemC based simulator. The distribution of packets is Poisson type with Buffer depth (number of buffers) of input channel FIFO is 8. Packet size is taken as 8 bytes. The simulation time is taken 50,000 cycles. We found that XY routing is better when the PIR is low. The partially adaptive routing is good when the PIR is moderate. DyAD routing is suited when the load i.e. PIR is high.

IOSR journal of VLSI and Signal Processing, 2014

Full adders are vital components in applications such as digital signal processors (DSP) architec... more Full adders are vital components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor FA using novel XOR and XNOR gates in combination with existing ones.We have done over ten thousand HSPICE simulation runs of the entire the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while 3 new adders consistently use on average 10% less power and have higher speed compared with the previous Ten-transistor full adder and the conventional 28-T CMOS adder. One draw back of the novel adders is the threshold-voltage loss of the pass transistors.

Micromachines

3D bioprinting has emerged as a tool for developing in vitro tissue models for studying disease p... more 3D bioprinting has emerged as a tool for developing in vitro tissue models for studying disease progression and drug development. The objective of the current study was to evaluate the influence of flow driven shear stress on the viability of cultured cells inside the luminal wall of a serpentine network. Fluid–structure interaction was modeled using COMSOL Multiphysics for representing the elasticity of the serpentine wall. Experimental analysis of the serpentine model was performed on the basis of a desirable inlet flow boundary condition for which the most homogeneously distributed wall shear stress had been obtained from numerical study. A blend of Gelatin-methacryloyl (GelMA) and PEGDA200 PhotoInk was used as a bioink for printing the serpentine network, while facilitating cell growth within the pores of the gelatin substrate. Human umbilical vein endothelial cells were seeded into the channels of the network to simulate the blood vessels. A Live-Dead assay was performed over a...

Neurocognitive Perspectives of Prosocial and Positive Emotional Behaviours, 2021

Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of... more Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of the same kinds of problems. This optimization technique does not suffer, however, from some of GA's difficulties; interaction in the group enhances rather than detracts from progress toward the solution. Further, a particle swarm system has memory, which the genetic algorithm does not have. In particle swarm optimization, individuals who fly past optima are tugged to return toward them; knowledge of good solutions is retained by all particles. The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm te...

Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of... more Particle swarm optimization (PSO) approach is used over genetic algorithms (GAS) to solve many of the same kinds of problems. This optimization technique does not suffer, however, from some of GA's difficulties; interaction in the group enhances rather than detracts from progress toward the solution. Further, a particle swarm system has memory, which the genetic algorithm does not have. In particle swarm optimization, individuals who fly past optima are tugged to return toward them; knowledge of good solutions is retained by all particles. The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm te...

Object tracking finds many practical applications ranging from robotics, surveillance, augmented ... more Object tracking finds many practical applications ranging from robotics, surveillance, augmented reality to human-computer computer interaction, the state state-of-the- art is still far from achieving results comparable to human performance. The goal of this article is to review the state-of-the-art art tracking methods. Object tracking remains a challenging problem due to appearance change caused by pose, illumination, occlusion, and motion, among others. An effective appearance model is of prime importance for the success of a tracking algorithm that has been attracting much attention in recent years. In this survey, we empirically demonstrate the performance of the algorithm against various common failure modes in the generic object tracking problem.

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy, 2014

Full adders are exigent components in applications such as digital signal processors (DSP) archit... more Full adders are exigent components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a new 11-transistor FA .We have done HSPICE simulation runs the new design 11-T full adders .In CMOS integrated circuit design there is a tradeoff between static power consumption and technology scaling. Static power dissipation is a challenge for the circuit designer. So we reduce the static power dissipation. In order to achieve lower static power consumption, one has to scarifies design area and circuit performance. In this paper we propose a new circuit of 11-Transistor full adder in CMOS VLSI circuit

Digital Signal Processing, 2016

The structure of the ECG signal is time varying which is the supreme common source used for the p... more The structure of the ECG signal is time varying which is the supreme common source used for the purpose of diagnosis & observation and analysis of various types of diseases related to the heart in the patient. ECG recording is the process done by placing the electrodes in the specified positions at body of humans. During the process of recording, a noise distracted signal is applied to ECG signal and the ECG signal is also full of artifacts which always degrades the quality of it and establishes threats in the recording the absolute ECG signal. The artifacts mostly noticed are Power line Interference, Baseline Wander and muscle tremors. Therefore, for accuracy in the characteristics points of ECG, an ECG having good quality is essential. Generally, we notice that these kinds of noises are very common in the process and detection is needed. We found that FIR-IIR filter is giving suitability to increase the quality of it. So, here we are presenting an implementation of the FIR-IIR fil...

Flow Dynamics and Tissue Engineering of Blood Vessels, 2020

Today’s testing of VLSI chips are very much complex day by day due to increasing advancement of n... more Today’s testing of VLSI chips are very much complex day by day due to increasing advancement of nano technology. So both front-end and back-end engineers are trying to evolve a system with full testability keeping in mind the possibility of reduced product failures and missed market opportunities. BIST is a testing technique that allows a system to test automatically itself. In this paper, the simulation result performance achieved by BIST enabled UART architecture through VHDL programming is shown. The BIST used here have two modes actually i.e. test mode and UART mode .This technique generate random test pattern automatically, so it can provide less test time compared to an externally applied test pattern and helps to achieve much more productivity at the end.

Programmable Device Circuits and Systems, 2017

A continuous increase in number of transistors and operating frequency causes high power dissipat... more A continuous increase in number of transistors and operating frequency causes high power dissipation. The most important task to minimize the power is optimization of power at the logic level. This paper presents a novel power efficient pulse triggered flip-flop. Proposed flip-flop use Exclusive-or gate based clock gating scheme that reduce the power dissipation by disabling the clock signal in inactive portion of chip. In this paper replica path delay pulse generator is used to simplify the design effort. This paper presents a comparison of existing flip-flop in term of power dissipation for different input patterns. The operation of flip-flop is analyzed and is simulated using Tanner EDA in 32nm technology at room temperature in schematic level. Simulation result shows the sensible power dissipation reduction.

The genetic algorithm works with the concept of chromosomes having gene where each gene act as a ... more The genetic algorithm works with the concept of chromosomes having gene where each gene act as a block of one solution. This is totally based on the solution which is followed by crossover and then mutation and finally reaches to fitness. The best fitness will be considered as a result and implemented in the practical area. Due to some drawbacks and problems exist in the genetic algorithm implemented, scientists moved to the other algorithm technique which is apparently based on the flock of birds moving to the target. This effectively overcome the shortcomings of GA and provides better fitness solutions to implement in the circuit.

Object tracking has been a very active research topic in the last few years due to its growing im... more Object tracking has been a very active research topic in the last few years due to its growing importance in various applications. Performance of object tracking can be reduces due to factors such as pose variation, illumination change, occlusion, and motion blur. Existing online algorithms often encounter problems such as drift and lack of data for learning. In this paper we presented an efficient online tracking algorithm with an appearance model based on multi scale image feature space with data independent basis. Proposed appearance model do not change the feature of object in iteration. Compound order samples of both background and foreground has been taken. These samples are reduced in size using sparse measurement matrix. Classification and updating of these samples is done in compressed domain. A MATLAB code has been implemented as per the proposed method and it gives us good result of tracking in simple and difficult sequences. Keywords—Compound Order Learning, Online Track...

Programmable Device Circuits and Systems, 2017

In past low power design techniques were not primary constraint because device density and operat... more In past low power design techniques were not primary constraint because device density and operating frequency were low. Nowadays because of very large scale integration, millions of transistors are fabricated on a single chip and requirement of high performance, portable, battery based devices causes need of low power design techniques. Digital circuits are two types: combinational circuit and sequential circuit. Sequential circuit mainly consists of flip-flops. Flip-flop is basic storage element and consume large amount of power because they are clocked with system operating frequency. Clock system consists of clock distribution network and flip-flops are most power consuming subsystems. Because of continuous increase in chip complexity and operating frequency reduction of power is long-winded task. After studying various journals and conferences, in this paper various low power Flip-flop design techniques are presented.

Programmable Device Circuits and Systems, 2017

This paper describes a low-power and lower-delay SRAM (Static Random- Access Memory) Cell using p... more This paper describes a low-power and lower-delay SRAM (Static Random- Access Memory) Cell using pulsed latch circuit. The delay and power consumption of conventional SRAM Cell is reduced by replacing two NMOS access transistors with pulsed latch circuit. The main aim of the pulsed latch circuit is to reduce delay and increase the speed of the design. As, SRAM Cell is one of the basic building element of VLSI design and due to its huge demand in VLSI chips, it is necessary to reduce power and delay so as to increases the speed of the SRAM Cell. In this paper 1bit, 4bit and 8bit SRAM Cell are designed with pulsed latch circuit and their performance is compared with conventional SRAM Cell design. The conventional SRAM and proposed SRAM Cell, both designs are implemented in 32nm CMOS technology with Vdd = 1.0V in Tanner tool v16.0. In comparision with conventional SRAM Cell the proposed SRAM Cell is much better in terms of power, speed and performance. In the proposed SRAM Cell design d...

Programmable Device Circuits and Systems, 2016

This paper presents a LNA for UWB radio receiver at 2 to 6GHz victimization 0.09µm TSMC Technolog... more This paper presents a LNA for UWB radio receiver at 2 to 6GHz victimization 0.09µm TSMC Technology wherever 009µm technology is for lower power consumption. UWB radio that created up in between the frequency vary of 2GHz to 6GHz.The basic design of LNA includes a RF electronic equipment within the middle of input matching network and also the output matching network. We’ve designed a LNA that consist low noise figure, good input and output resistivity matching and high gain and stability LNA, wherever operative temperature is 27 oC gain is 20dB and would have smart stability. we have a tendency to used ltspice tool for the simplest performance and accuracy for results, this work represents associate LNA schematic compose of Common source LNA and Cascode LNA, wherever Common source LNA is employed for glorious input and output matching and also the cascode LNA for low Noise figure and high gain, an extra feature is that single terminated LNA employs inductive supply degeneration conc...

Artificial Intelligent Systems and Machine Learning, 2016

In this paper we work on the control of total power consumption of a low noise amplifier using un... more In this paper we work on the control of total power consumption of a low noise amplifier using unique design of CMOS active inductor (on chip) for the low voltage RF circuit. We tried to address a replacement methodology of passive inductors by Active Inductors (AI) to improve the circuit performance. And improved parameter like power potency, Noise Figure (NF) and alternate methodology of input and output matching of 50 ohm. Exploiting the new biasing metric, and new design methodology of 1.8v supply, leads to 5.4mW total DC power consumption. We uses 180nm CMOS technology, frequency range of 2-6GHz. This simulation offers the thought of the longer term analysis to design higher LNA in terms of low power consumption, stability and higher range of frequency of operation.

Object tracking finds many practical applications r anging from robotics, surveillance, augmented... more Object tracking finds many practical applications r anging from robotics, surveillance, augmented reali ty to computer interaction, the state -of-the- art is still far from achieving results comparable to human performance. The goal of this article is t o review the state-of-the- art tracking methods. Object tracking remains a challenging problem due to appearance change caused by pose, illumination, occlusion, and motion, amon g others. An effective appearance model is of prime importance for the success o f a tracking algorithm that has been attracting much attention in recent years. In this survey, we empirically demonstrate the performance of the algorithm against various common failure modes in t he generic object tracking problem.

International Journal of Emerging Trends in Science and Technology, May 27, 2014

Network on Chip (NoC) is a new paradigm for making interconnections within System on Chip (SoC) s... more Network on Chip (NoC) is a new paradigm for making interconnections within System on Chip (SoC) system. With the increasing chip integration and decreasing feature size the SoC does not meet the challenges of the new process technologies .The challenges include complexity and increased delay in communication and also the bus contention and arbitration slows down the data movement which degrades the overall performance of Soc. Noc is a design platform that can meet these challenges to a great extend. In the network design of the NoC the most essential things are a network topology and a routing algorithm. Routers route the packets based on the algorithm that they use. In this paper a study of the different routing algorithms for network on chip is presented that can cope up with above mentioned problems arising in SoC. The routing algorithm of a given NoC system is measured with respect to performance metrics such as latency, throughput and load distribution. Here we are about to deal with the different topologies ,switching techniques ,performance analysis of NoC routing algorithms such as XY routing algorithm, OE routing algorithm and DyAD routing algorithm . keywords- NoC , Routers, routing algorithms, latency, throughput, XY ,OE , DyAD

Springer Proceedings in Physics, 2015

Network on Chip (NoC) is an on-chip communication technology in which a large number of processin... more Network on Chip (NoC) is an on-chip communication technology in which a large number of processing elements and storage blocks are integrated on a single chip. Due to scalability, adaptive nature, well resource utilization NoCs have become popular in and has efficiently replaced SoCs. NoCs performance depends mainly on the type of routing algorithm chosen. In this paper three different types of routing algorithms are being compared firstly one is deterministic routing (XY routing algorithm), secondly three partially adaptive routing (West-first, North-last and Negative-first) and two adaptive routing (DyAD, OE) are being compared with respect to Packet Injection Rate (PIR) of load for random traffic pattern for 4 × 4 mesh topology. All these comparison and simulation is done in NOXIM 2.3.1 simulator which is a cycle accurate systemC based simulator. The distribution of packets is Poisson type with Buffer depth (number of buffers) of input channel FIFO is 8. Packet size is taken as 8 bytes. The simulation time is taken 50,000 cycles. We found that XY routing is better when the PIR is low. The partially adaptive routing is good when the PIR is moderate. DyAD routing is suited when the load i.e. PIR is high.

IOSR journal of VLSI and Signal Processing, 2014

Full adders are vital components in applications such as digital signal processors (DSP) architec... more Full adders are vital components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor FA using novel XOR and XNOR gates in combination with existing ones.We have done over ten thousand HSPICE simulation runs of the entire the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while 3 new adders consistently use on average 10% less power and have higher speed compared with the previous Ten-transistor full adder and the conventional 28-T CMOS adder. One draw back of the novel adders is the threshold-voltage loss of the pass transistors.