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Papers by Dr. Idrees Al-kofahi

International Journal of Electrical and Computer Engineering (IJECE), 2021

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz ... more In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 μm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of 3dBm. Keywords— 0.18μm CMOS technology, Boosting inductors, Gain, Linearity, Partial source degeneration PSD, Radio frequency identificatio...

Journal of Applied Physics, 1997

ABSTRACT This article reports new experimental results on the continuing interface trap generatio... more ABSTRACT This article reports new experimental results on the continuing interface trap generation post-hot hole injection and investigates the generation mechanism. The generation post-hole injection is found to be two orders of magnitude slower than that post-irradiation and cannot be satisfactorily explained by the transportation of hydrogen species across the gate oxide. The role played by the recombination of trapped holes with free electrons is examined. There is a lack of correlation between the trapped hole removal and the interface trap creation, which is against the prediction of the trapped hole conversion model. The results indicate that the interface traps generated during and post-stress originate from two different defects. The defect responsible for post-stress generation is excited by hole injection and then converted into an interface trap if a positive gate bias is applied. It is found that generation in a poly-Si gated metal–oxide–semiconductor field effect transistor behaves differently from that in an Al-gated device. The possible causes for this difference are discussed. © 1997 American Institute of Physics.

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 µm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of-3dBm.

Received 11-02-2013, accepted 20-02-2013, online 21-02-2013 Abstract In this paper the reliabilit... more Received 11-02-2013, accepted 20-02-2013, online 21-02-2013 Abstract In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique is considered. The technologically important low field case (Eox<2 MV/cm) for a current densities range from 0.02 to 2 mA/cm 2 and injected charge densities up to 10 C/cm2 is considered here in some detail. We confirm previous results reported by ourselves and others that there is a dependence of oxide degradation upon the current density during SHE injection. The dynamic trapping and detrapping of previously trapped electrons are taken into account to explain these results. A power law model is presented which accounts for the detrapping phenomenon. Genetic algorithm is used to extract the parameters of the model.

In this paper the transmission limitations due to the fiber loss and dispersion in optical networ... more In this paper the transmission limitations due to the fiber loss and dispersion in optical networks have been investigated, theoretically and experimentally, for three different fibers. An approach for computing the maximum allowable transmission distance imposed by the fiber loss and dispersion as a function of bit rate has been developed. It is found that fiber loss is the dominant factor that determine maximum allowable transmission distance at low bit rate. However, as the bit rate increases, fiber dispersion rather than fiber loss is the factor which determines the maximum allowable transmission distance. By comparing the three fibers under study, it is found that, 850nm fiber is the worst in terms of transmission distance, while the 1550nm has superiority over the 1330nm for bit rate <9.5Gb/s. However, for bit rate>9.5Gb/s the 1330nm fiber is better in terms of bit rate and transmission distance. Experimental results for the three fibers (850nm, 1300nm and 1550nm) show a...

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 µm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of-3dBm.

International Journal of Electrical and Computer Engineering (IJECE), 2021

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz ... more In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about-5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed. Keywords: CMOS Low noise amplifier Power amplifier Topologies Ultra-wideband (UWB) This is an open access article under the CC BY-SA license.

Journal of Electroanalytical Chemistry, 2011

The fourth and higher harmonic components available in large-amplitude Fourier transformed ac vol... more The fourth and higher harmonic components available in large-amplitude Fourier transformed ac voltammetry have been employed in a study involving surface-confined redox proteins having multiple electron-transfer centers. Ferredoxin I from Azotobacter vinelandii (AvFdI) and two variants exhibit significant differences in the reversible reduction potentials (Eo′) of their two non-interacting FeS clusters which are located at a fixed distance 1.2nm apart.

International Journal of Emerging Trends in Engineering Research

In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) techniq... more In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique is considered. The technologically important low field case (E ox <2 MV/cm) for a current densities range from 0.02 to 2 mA/cm 2 and injected charge densities up to 10 C/cm 2 is considered here in some detail. We confirm previous results reported by ourselves and others that there is a dependence of oxide degradation upon the current density during SHE injection. The dynamic trapping and detrapping of previously trapped electrons are taken into account to explain these results. A power law model is presented which accounts for the detrapping phenomenon. Genetic algorithm is used to extract the parameters of the model.

Defects created in p-metal-oxide-semiconductor-field-effect transistors by substrate-hole injecti... more Defects created in p-metal-oxide-semiconductor-field-effect transistors by substrate-hole injection are studied. Both fast and slow interface states are found to be created during the holes injection process. After terminating the stress and applying positive gate bias, fast interface states are found to keep increasing, while slow states reduction and trapped holes annihi-lation are observed. The build up of fast interface states during and post stress is a consequence of holes injection and annihilation. However, the trapped holes have no influence on the number of slow states present in the oxide. The effect of trapped holes annihilation on both fast and slow states suggests that their formation mechanisms are not the same.

2005 International Conference on Microelectronics, 2005

ABSTRACT The damage created in p-metal-oxide-semiconductor-field-effect (p-MOSFET) transistors by... more ABSTRACT The damage created in p-metal-oxide-semiconductor-field-effect (p-MOSFET) transistors by hot hole injection into the oxide is investigated. It is found that hole injection creates fast interface states not only during the injection, but also after the injection is terminated. In addition, slow state density increases during hole injection and decreases post the injection. There is a lack of correlation between the trapped holes in the oxide and the slow state creation, which is against recently reported results on trapped holes inducing slow interface states in MOSFETs.

Proceedings of International Reliability Physics Symposium RELPHY-96, 1996

ABSTRACT The recently reported post-stress degradation of MOSFETs is investigated in more detail ... more ABSTRACT The recently reported post-stress degradation of MOSFETs is investigated in more detail in this paper. The interface trap generation post hole injection is found to be two orders of magnitude slower than that post-irradiation and cannot be satisfactorily explained by the transportation of hydrogen species across the bulk of oxide. There is a lack of correlation between the trapped hole removal and the interface trap creation, which is against the prediction of the trapped hole conversion model. It is found that the interface traps generated during and post the stress originate from two different defects. The defect responsible for the post-stress generation is excited by the hole injection and then converted into an interface trap if a positive gate bias is applied post-stress.

2008 IEEE International Conference on Semiconductor Electronics, 2008

ABSTRACT Reported here are subthreshold measurements on n-channel 6H-SiC MOSFETs over a range of ... more ABSTRACT Reported here are subthreshold measurements on n-channel 6H-SiC MOSFETs over a range of temperatures. A simple theoretical model is presented to explain their general form. It is shown that the temperature dependence of the subthreshold current indicates a high density of electronic states at or near the SiC-SiO 2 interface. These states are negatively charged when occupied (acceptor-like), and emit their trapped electrons at elevated temperatures. They are believed to be responsible for the observed shift in the subthreshold characteristics at higher temperatures.

Superlattices and Microstructures, 2005

The genetic algorithm method has been applied to analyze experimental photoluminescence data from... more The genetic algorithm method has been applied to analyze experimental photoluminescence data from interdiffused quantum well heterostructures. It has been shown that this method offers a direct determination of the interdiffusion activation energy (Ea) and prefactor (Dˆ), without the need for the Arrhenius plot. These interdiffusion parameters, determined using the genetic algorithm method, were shown to be comparable with those obtained by the least-squares analysis method. Any extrinsic interdiffusion process was shown to be detected more clearly when using the genetic algorithm method unlike the least-squares analysis which was shown to draw, in some cases, unreliable conclusions.

International Journal of Electrical and Computer Engineering (IJECE), 2021

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz ... more In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about -5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed.

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 μm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of 3dBm. Keywords— 0.18μm CMOS technology, Boosting inductors, Gain, Linearity, Partial source degeneration PSD, Radio frequency identificatio...

Journal of Applied Physics, 1997

ABSTRACT This article reports new experimental results on the continuing interface trap generatio... more ABSTRACT This article reports new experimental results on the continuing interface trap generation post-hot hole injection and investigates the generation mechanism. The generation post-hole injection is found to be two orders of magnitude slower than that post-irradiation and cannot be satisfactorily explained by the transportation of hydrogen species across the gate oxide. The role played by the recombination of trapped holes with free electrons is examined. There is a lack of correlation between the trapped hole removal and the interface trap creation, which is against the prediction of the trapped hole conversion model. The results indicate that the interface traps generated during and post-stress originate from two different defects. The defect responsible for post-stress generation is excited by hole injection and then converted into an interface trap if a positive gate bias is applied. It is found that generation in a poly-Si gated metal–oxide–semiconductor field effect transistor behaves differently from that in an Al-gated device. The possible causes for this difference are discussed. © 1997 American Institute of Physics.

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 µm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of-3dBm.

Received 11-02-2013, accepted 20-02-2013, online 21-02-2013 Abstract In this paper the reliabilit... more Received 11-02-2013, accepted 20-02-2013, online 21-02-2013 Abstract In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique is considered. The technologically important low field case (Eox<2 MV/cm) for a current densities range from 0.02 to 2 mA/cm 2 and injected charge densities up to 10 C/cm2 is considered here in some detail. We confirm previous results reported by ourselves and others that there is a dependence of oxide degradation upon the current density during SHE injection. The dynamic trapping and detrapping of previously trapped electrons are taken into account to explain these results. A power law model is presented which accounts for the detrapping phenomenon. Genetic algorithm is used to extract the parameters of the model.

In this paper the transmission limitations due to the fiber loss and dispersion in optical networ... more In this paper the transmission limitations due to the fiber loss and dispersion in optical networks have been investigated, theoretically and experimentally, for three different fibers. An approach for computing the maximum allowable transmission distance imposed by the fiber loss and dispersion as a function of bit rate has been developed. It is found that fiber loss is the dominant factor that determine maximum allowable transmission distance at low bit rate. However, as the bit rate increases, fiber dispersion rather than fiber loss is the factor which determines the maximum allowable transmission distance. By comparing the three fibers under study, it is found that, 850nm fiber is the worst in terms of transmission distance, while the 1550nm has superiority over the 1330nm for bit rate <9.5Gb/s. However, for bit rate>9.5Gb/s the 1330nm fiber is better in terms of bit rate and transmission distance. Experimental results for the three fibers (850nm, 1300nm and 1550nm) show a...

A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulate... more A high gain CMOS Low Noise Amplifier (LNA) for 866 MHz RFID reader has been proposed and simulated in 0.18 µm CMOS technology. A new energy efficient technique along with the current bleeding PMOS devices has been used to reduce the leakage power of the RF signal and increase the gain of the proposed LNA design. Furthermore, the folded cascode with a combination of the partial source degeneration (PSD) is improved; and the current and boosting inductor are reused to enhance the gain and linearity of the proposed design. The simulation results show that the proposed LNA design outperforms the conventional fold cascode LNA in terms of gain (S21) and Noise Figure (NF). The proposed LNA achieves a forward gain of 24.8 dB with a NF of 0.38 dB with 10.6mW drawn from a 1.2V source supply; and a high linearity Input Third-Order Intercept Point (IIP3) of-3dBm.

International Journal of Electrical and Computer Engineering (IJECE), 2021

In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz ... more In this paper, a two-stage 0.18 μm CMOS power amplifier (PA) for ultra-wideband (UWB) 3 to 5 GHz based on common source inductive degeneration with an auxiliary amplifier is proposed. In this proposal, an auxiliary amplifier is used to place the 2nd harmonic in the core amplified in order to make up for the gain progression phenomena at the main amplifier output node. Simulation results show a power gain of 16 dB with a gain flatness of 0.4 dB and an input 1 dB compression of about-5 dBm from 3 to 5 GHz using a 1.8 V power supply consuming 25 mW. Power added efficiency (PAE) of around 47% at 4 GHz with 50 Ω load impedance was also observed. Keywords: CMOS Low noise amplifier Power amplifier Topologies Ultra-wideband (UWB) This is an open access article under the CC BY-SA license.

Journal of Electroanalytical Chemistry, 2011

The fourth and higher harmonic components available in large-amplitude Fourier transformed ac vol... more The fourth and higher harmonic components available in large-amplitude Fourier transformed ac voltammetry have been employed in a study involving surface-confined redox proteins having multiple electron-transfer centers. Ferredoxin I from Azotobacter vinelandii (AvFdI) and two variants exhibit significant differences in the reversible reduction potentials (Eo′) of their two non-interacting FeS clusters which are located at a fixed distance 1.2nm apart.

International Journal of Emerging Trends in Engineering Research

In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) techniq... more In this paper the reliability of n-channel MOSFETs using the Substrate Hot Electron (SHE) technique is considered. The technologically important low field case (E ox <2 MV/cm) for a current densities range from 0.02 to 2 mA/cm 2 and injected charge densities up to 10 C/cm 2 is considered here in some detail. We confirm previous results reported by ourselves and others that there is a dependence of oxide degradation upon the current density during SHE injection. The dynamic trapping and detrapping of previously trapped electrons are taken into account to explain these results. A power law model is presented which accounts for the detrapping phenomenon. Genetic algorithm is used to extract the parameters of the model.

Defects created in p-metal-oxide-semiconductor-field-effect transistors by substrate-hole injecti... more Defects created in p-metal-oxide-semiconductor-field-effect transistors by substrate-hole injection are studied. Both fast and slow interface states are found to be created during the holes injection process. After terminating the stress and applying positive gate bias, fast interface states are found to keep increasing, while slow states reduction and trapped holes annihi-lation are observed. The build up of fast interface states during and post stress is a consequence of holes injection and annihilation. However, the trapped holes have no influence on the number of slow states present in the oxide. The effect of trapped holes annihilation on both fast and slow states suggests that their formation mechanisms are not the same.

2005 International Conference on Microelectronics, 2005

ABSTRACT The damage created in p-metal-oxide-semiconductor-field-effect (p-MOSFET) transistors by... more ABSTRACT The damage created in p-metal-oxide-semiconductor-field-effect (p-MOSFET) transistors by hot hole injection into the oxide is investigated. It is found that hole injection creates fast interface states not only during the injection, but also after the injection is terminated. In addition, slow state density increases during hole injection and decreases post the injection. There is a lack of correlation between the trapped holes in the oxide and the slow state creation, which is against recently reported results on trapped holes inducing slow interface states in MOSFETs.

Proceedings of International Reliability Physics Symposium RELPHY-96, 1996

ABSTRACT The recently reported post-stress degradation of MOSFETs is investigated in more detail ... more ABSTRACT The recently reported post-stress degradation of MOSFETs is investigated in more detail in this paper. The interface trap generation post hole injection is found to be two orders of magnitude slower than that post-irradiation and cannot be satisfactorily explained by the transportation of hydrogen species across the bulk of oxide. There is a lack of correlation between the trapped hole removal and the interface trap creation, which is against the prediction of the trapped hole conversion model. It is found that the interface traps generated during and post the stress originate from two different defects. The defect responsible for the post-stress generation is excited by the hole injection and then converted into an interface trap if a positive gate bias is applied post-stress.

2008 IEEE International Conference on Semiconductor Electronics, 2008

ABSTRACT Reported here are subthreshold measurements on n-channel 6H-SiC MOSFETs over a range of ... more ABSTRACT Reported here are subthreshold measurements on n-channel 6H-SiC MOSFETs over a range of temperatures. A simple theoretical model is presented to explain their general form. It is shown that the temperature dependence of the subthreshold current indicates a high density of electronic states at or near the SiC-SiO 2 interface. These states are negatively charged when occupied (acceptor-like), and emit their trapped electrons at elevated temperatures. They are believed to be responsible for the observed shift in the subthreshold characteristics at higher temperatures.

Superlattices and Microstructures, 2005

The genetic algorithm method has been applied to analyze experimental photoluminescence data from... more The genetic algorithm method has been applied to analyze experimental photoluminescence data from interdiffused quantum well heterostructures. It has been shown that this method offers a direct determination of the interdiffusion activation energy (Ea) and prefactor (Dˆ), without the need for the Arrhenius plot. These interdiffusion parameters, determined using the genetic algorithm method, were shown to be comparable with those obtained by the least-squares analysis method. Any extrinsic interdiffusion process was shown to be detected more clearly when using the genetic algorithm method unlike the least-squares analysis which was shown to draw, in some cases, unreliable conclusions.