Dr. Mohsin Tarar - Academia.edu (original) (raw)

Papers by Dr. Mohsin Tarar

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

This work presents the design and implementation of a fully integrated broadband medium power sta... more This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull -1 dB, -2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm2.

Stacked inverter-based amplifier with bandwidth enhancement by inductive peaking

ABSTRACT This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technol... more ABSTRACT This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technology. The proposed amplifier, based on an inverter, uses stacking to achieve high output swing and distributed inductive peaking to obtain ultra-wide bandwidth. Furthermore, the proposed topology is generalized for more stacked transistors for high output swing requirement which then utilizes distributive peaking inductors to maintain that swing over a large bandwidth. The simulated output swing for a 2-, 4- and 6-stacked amplifier is 4.0 V, 6.5 V and 8.0 V with 3 dB-voltage bandwidth of 50 GHz, 43 GHz and 41.5 GHz, respectively. All transistors are regular RF MOSFETs with a 1.2 V supply voltage.

Analog Integrated Circuits and Signal Processing, Aug 3, 2016

In this paper, we present analysis, design and show experimental results of a new type of CMOS ba... more In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are commonsource (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P 1 dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 % is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than-30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 %. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Design and implementation of an electrical interface for ring modulators using CPWs

German Microwave Conference, Mar 10, 2014

This work presents the design and implementation of an electrical interface using coplanar wavegu... more This work presents the design and implementation of an electrical interface using coplanar waveguides (CPWs) to drive high speed ring modulators. To show this, first a small-signal model (SSM) of the modulator is developed by measuring its S11 response. The SSM is simulated with a conventional CPW to highlight the reflection problem emerging from the mismatch between the 50 Omega system reference and the high input impedance of the ring modulator which is around 1kOmega. The mismatch problem is mitigated by the proposed five-pin CPW design with ground-signalground- signal-ground (GSGSG) structure which terminates the reflection into an external 50 Omega termination. The proposed CPW demonstrates a measured S11 magnitude response below -15 dB throughout the frequency range of 25 GHz and -10 dB until 40 GHz.

Asymmetric Doherty power amplifier at 2.2 GHz with 8.2 dB output power back-off

German Microwave Conference, Mar 12, 2012

This work presents the design and implementation of a 10 W asymmetric Doherty power amplifier (AD... more This work presents the design and implementation of a 10 W asymmetric Doherty power amplifier (ADPA) with 8.2 dB back-off at 2.2 GHz in Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) technology. The amplifier was designed to achieve high efficiency over an increased dynamic range for applications with high peak-to-average power ratios (PAPRs). In order to obtain high efficiency

Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

This work presents the design and implementation of a flat-gain, efficient and wideband stacked d... more This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 −16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

Efficient amplification of signals with high PAPR using a novel multilevel LINC transmitter architecture

ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter a... more ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter architecture. The proposed system is able to provide a large number of reconfigurable multiple levels by arbitrarily controlling the output power of the two efficient power amplifiers. The novelty of the architecture relies in the efficient generation of the arbitrary multilevels. In fact, the system uses only one fixed supply voltage. An algorithm is developed to optimise the different symmetrical levels depending on the actual signal statistics in order to boost average system efficiency. A multilevel LINC transmitter system demonstrator was build to validate the proposed concept. Besides The system employs two identical hybrid power amplifiers designed using GaN HEMTs for a centre frequency of 2.28 GHz and output power of 40 dBm, the system employs only off-the-shelf components or measurement equipment. Measurement results on the demonstrator show that compared with a conventional LINC transmitter, average power efficiency of the proposed system can be improved from 28 % to 41 % for a WCDMA signal with a measured adjacent-channel-power ratio (ACPR) below -45 dBc. For a 10 MHz LTE signal efficiency is improved by nearly 24 percentage-points compared with a regular LINC system.

Enhanced gain bandwidth and loss compensated cascaded single-stage CMOS distributed amplifier

This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in comm... more This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in commercial 65nm CMOS technology. The CSSDA is composed of three distributed stages connected in a cascade configuration to target high gain. The idle interstage drain terminations are omitted because of multiplicative gain mechanism. High gain is maintained over very large bandwidth through the inductive-peaking technique. Further, the CSSDA single cell is modified by a loss compensation technique to remove the high frequency losses of the artificial transmission lines which shows a significant enhancement in gain bandwidth (GBW) product. The simulation results show a GBW of 540GHz for the loss compensated CSSDA (LC-CSSDA) which is significantly higher than GBW of 350 GHz for a conventional CSSDA. The 2-stage (LC-CSSDA) shows a GBW of 835GHz which is almost twice the GBW (426 GHz) of a conventional 2-stage CSSDA.

IEEE Access

This work presents the analysis, design, and implementation of an efficient and wideband active-s... more This work presents the analysis, design, and implementation of an efficient and wideband active-split dual-feed distributed amplifier (AS-DFDA) in 0.13µm CMOS technology. It consists of a dualfeed (DF) output stage with a passive combiner and an active-split (AS) input stage. The dual-feed stage is used to enhance the gain and output power of the proposed AS-DFDA by utilising both the forward and reverse gains of a conventional distributed topology. The DF stage requires an in-phase equi-amplitude signals feeding the DF gate lines from both sides which is accomplished by an active-split stage based on the split drain-line topology providing a wideband input match along with the extra leaverage in gain. An external capacitance in series with the DF stage devices is deployed to increase the cutoff frequency of the dual-feed gate lines. Further, the interstage lines are terminated with idle-line terminations on both ends to target flat gain. The amplified signal from DF stage is combined through an output impedance matched direct passive combiner. The measured results show a 13-10 dB gain from 4-22 GHz and output return loss of 6dB over the entire bandwidth. The measured output saturated power, P SAT , of 10.6 dBm with peak power added efficiency (PAE) of 15.1% is acheived at 5 GHz while a minimum peak PAE of 9% is obtained over the entire bandwidth. The AS-DFDA has a noise figure of 4-6 dB and occupies an active area of only 0.45 mm 2 , respectively.

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

Efficient amplification of signals with high PAPR using a novel multilevel LINC transmitter architecture

2012 42nd European Microwave Conference, 2012

ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter a... more ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter architecture. The proposed system is able to provide a large number of reconfigurable multiple levels by arbitrarily controlling the output power of the two efficient power amplifiers. The novelty of the architecture relies in the efficient generation of the arbitrary multilevels. In fact, the system uses only one fixed supply voltage. An algorithm is developed to optimise the different symmetrical levels depending on the actual signal statistics in order to boost average system efficiency. A multilevel LINC transmitter system demonstrator was build to validate the proposed concept. Besides The system employs two identical hybrid power amplifiers designed using GaN HEMTs for a centre frequency of 2.28 GHz and output power of 40 dBm, the system employs only off-the-shelf components or measurement equipment. Measurement results on the demonstrator show that compared with a conventional LINC transmitter, average power efficiency of the proposed system can be improved from 28 % to 41 % for a WCDMA signal with a measured adjacent-channel-power ratio (ACPR) below -45 dBc. For a 10 MHz LTE signal efficiency is improved by nearly 24 percentage-points compared with a regular LINC system.

Efficient and wideband CMOS distributed power amplifiers for various high data rate applications

Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

2017 IEEE MTT-S International Microwave Symposium (IMS), 2017

This work presents the design and implementation of a flat-gain, efficient and wideband stacked d... more This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 −16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

A −115 dBc/Hz Integrated Optoelectronic Oscillator in a BiCMOS Silicon Photonic Technology

2021 IEEE MTT-S International Microwave Symposium (IMS), 2021

An optoelectronic oscillator implemented in a 250 nm SiGe BiCMOS Silicon photonic technology is p... more An optoelectronic oscillator implemented in a 250 nm SiGe BiCMOS Silicon photonic technology is presented. It features a monolithic integration of the electronic amplifier components, the electro-optical modulator and the photodiode to achieve a low-parasitics and compact solution on a single chip. A phase noise of −115 dBc/Hz at a frequency offset of 100 kHz from the fundamental frequency of 750 MHz was measured. The phase noise is among the lowest for monolithically integrated optoelectronic oscillators. The frequency response gives a promising outlook to future fully monolithic integrated optoelectronic oscillators when a low loss micro-resonator is utilized to simultaneously act as an optical delay element and filter at frequencies above 20 GHz.

Analog Integrated Circuits and Signal Processing, 2016

This work presents the design and implementation of a fully integrated and compact broadband medi... more This work presents the design and implementation of a fully integrated and compact broadband medium stacked power amplifier in standard 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack at the output to primarily increase the output impedance along with the output voltage swing. The load impedance is further optimized with a resistive feedback to the input active device which not only results in broadband operation but also helps in avoiding large and lossy broadband output matching network, resulting in a significant area reduction. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier works directly into a 50X load and shows a measured peak saturated output power from 13 to 8.5 dBm and a P 1dB of 7-4 dBm from 0.3 to 10 GHz. The drain and peak power added efficiency are 6.5 and 4.3 % under 4 V supply with DC power consumption of 160 mW. The measured small signal gain is around 9 dB with a gain ripple of ±1.5 dB till 7 GHz and 5.4 dB at 10 GHz, yielding a fractional bandwidth of 188 %. The measured load-pull-1 dB,-2 dB output power contours verify the optimum impedance around 50 X. The active chip area is only 0.44 mm 2 .

IEEE Transactions on Microwave Theory and Techniques, 2017

This paper presents the design and implementation of efficient and wideband stacked distributed p... more This paper presents the design and implementation of efficient and wideband stacked distributed power amplifiers (SDPAs) in 0.13-µm CMOS technology. To obtain high output swing along with reasonable gain, a four-transistor stack is utilized. Voltage alignment at the drain of each device in the stack is obtained by allowing a small ac swing at the gate due to voltage division between the gate-source capacitance, C gs , and the external gate capacitance. Interstage matching is performed by peaking inductors. Further, the four-transistor stack has been replicated in four sections in a distributed topology to obtain wideband operation. A uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines. Based on the said approach, two topologies, the SDPA and the stackedcascode distributed power amplifier (SCDPA), are designed, implemented, and compared in terms of their performance. For SDPA, measured results show at least 10 ± 0.3 dB of small-signal gain from 2 to 16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with a peak efficiency of 17% and an OIP3 of 22 dBm. The SCDPA shows a measured small-signal gain of more than 10 dB at low frequencies and drops to 10 dB at 10 GHz. Also, the SCDPA demonstrates a saturated output power of 19.8 dBm with a peak efficiency of 19% and an OIP3 of 23 dBm. Both power amplifiers occupy an area of 0.83 mm 2 .

Analysis and design of class-O RF power amplifiers for wireless communication systems

Analog Integrated Circuits and Signal Processing, 2016

In this paper, we present analysis, design and show experimental results of a new type of CMOS ba... more In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are common-source (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P$$_{1\,{\mathrm{dB}}}$$1dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 \%$$% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than −30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 \%$$%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Design and implementation of an electrical interface for ring modulators using CPWs

This work presents the design and implementation of an electrical interface using coplanar wavegu... more This work presents the design and implementation of an electrical interface using coplanar waveguides (CPWs) to drive high speed ring modulators. To show this, first a small-signal model (SSM) of the modulator is developed by measuring its S11 response. The SSM is simulated with a conventional CPW to highlight the reflection problem emerging from the mismatch between the 50 Omega system reference and the high input impedance of the ring modulator which is around 1kOmega. The mismatch problem is mitigated by the proposed five-pin CPW design with ground-signalground- signal-ground (GSGSG) structure which terminates the reflection into an external 50 Omega termination. The proposed CPW demonstrates a measured S11 magnitude response below -15 dB throughout the frequency range of 25 GHz and -10 dB until 40 GHz.

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

A compact 0.3–10 GHz broadband stacked amplifier in 65nm standard CMOS

This work presents the design and implementation of a fully integrated broadband medium power sta... more This work presents the design and implementation of a fully integrated broadband medium power stacked amplifier in 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack to increase the output voltage swing along with the output impedance. The load impedance is further optimized with a resistive feedback which not only results in broadband operation but also avoids a lossy broadband output matching network which reduces area significantly. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier shows a measured peak saturated output power from 13 dBm to 8.5 dBm and a P1dB of 7 dBm to 4 dBm from 0.3 GHz to 10 GHz. The measured gain is 9 dB with a gain ripple of ±1.5 dB in the entire frequency range, yielding a fractional bandwidth of 188%. The measured load-pull -1 dB, -2 dB output power contours verify the optimum impedance around 50 Ω. The active chip area is only 0.44mm2.

Stacked inverter-based amplifier with bandwidth enhancement by inductive peaking

ABSTRACT This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technol... more ABSTRACT This paper presents a stacked inverter-based amplifier in a commercial 65nm CMOS technology. The proposed amplifier, based on an inverter, uses stacking to achieve high output swing and distributed inductive peaking to obtain ultra-wide bandwidth. Furthermore, the proposed topology is generalized for more stacked transistors for high output swing requirement which then utilizes distributive peaking inductors to maintain that swing over a large bandwidth. The simulated output swing for a 2-, 4- and 6-stacked amplifier is 4.0 V, 6.5 V and 8.0 V with 3 dB-voltage bandwidth of 50 GHz, 43 GHz and 41.5 GHz, respectively. All transistors are regular RF MOSFETs with a 1.2 V supply voltage.

Analog Integrated Circuits and Signal Processing, Aug 3, 2016

In this paper, we present analysis, design and show experimental results of a new type of CMOS ba... more In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are commonsource (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P 1 dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 % is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than-30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 %. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Design and implementation of an electrical interface for ring modulators using CPWs

German Microwave Conference, Mar 10, 2014

This work presents the design and implementation of an electrical interface using coplanar wavegu... more This work presents the design and implementation of an electrical interface using coplanar waveguides (CPWs) to drive high speed ring modulators. To show this, first a small-signal model (SSM) of the modulator is developed by measuring its S11 response. The SSM is simulated with a conventional CPW to highlight the reflection problem emerging from the mismatch between the 50 Omega system reference and the high input impedance of the ring modulator which is around 1kOmega. The mismatch problem is mitigated by the proposed five-pin CPW design with ground-signalground- signal-ground (GSGSG) structure which terminates the reflection into an external 50 Omega termination. The proposed CPW demonstrates a measured S11 magnitude response below -15 dB throughout the frequency range of 25 GHz and -10 dB until 40 GHz.

Asymmetric Doherty power amplifier at 2.2 GHz with 8.2 dB output power back-off

German Microwave Conference, Mar 12, 2012

This work presents the design and implementation of a 10 W asymmetric Doherty power amplifier (AD... more This work presents the design and implementation of a 10 W asymmetric Doherty power amplifier (ADPA) with 8.2 dB back-off at 2.2 GHz in Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) technology. The amplifier was designed to achieve high efficiency over an increased dynamic range for applications with high peak-to-average power ratios (PAPRs). In order to obtain high efficiency

Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

This work presents the design and implementation of a flat-gain, efficient and wideband stacked d... more This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 −16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

Efficient amplification of signals with high PAPR using a novel multilevel LINC transmitter architecture

ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter a... more ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter architecture. The proposed system is able to provide a large number of reconfigurable multiple levels by arbitrarily controlling the output power of the two efficient power amplifiers. The novelty of the architecture relies in the efficient generation of the arbitrary multilevels. In fact, the system uses only one fixed supply voltage. An algorithm is developed to optimise the different symmetrical levels depending on the actual signal statistics in order to boost average system efficiency. A multilevel LINC transmitter system demonstrator was build to validate the proposed concept. Besides The system employs two identical hybrid power amplifiers designed using GaN HEMTs for a centre frequency of 2.28 GHz and output power of 40 dBm, the system employs only off-the-shelf components or measurement equipment. Measurement results on the demonstrator show that compared with a conventional LINC transmitter, average power efficiency of the proposed system can be improved from 28 % to 41 % for a WCDMA signal with a measured adjacent-channel-power ratio (ACPR) below -45 dBc. For a 10 MHz LTE signal efficiency is improved by nearly 24 percentage-points compared with a regular LINC system.

Enhanced gain bandwidth and loss compensated cascaded single-stage CMOS distributed amplifier

This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in comm... more This work presents a loss compensated cascaded single-stage distributed amplifier (CSSDA) in commercial 65nm CMOS technology. The CSSDA is composed of three distributed stages connected in a cascade configuration to target high gain. The idle interstage drain terminations are omitted because of multiplicative gain mechanism. High gain is maintained over very large bandwidth through the inductive-peaking technique. Further, the CSSDA single cell is modified by a loss compensation technique to remove the high frequency losses of the artificial transmission lines which shows a significant enhancement in gain bandwidth (GBW) product. The simulation results show a GBW of 540GHz for the loss compensated CSSDA (LC-CSSDA) which is significantly higher than GBW of 350 GHz for a conventional CSSDA. The 2-stage (LC-CSSDA) shows a GBW of 835GHz which is almost twice the GBW (426 GHz) of a conventional 2-stage CSSDA.

IEEE Access

This work presents the analysis, design, and implementation of an efficient and wideband active-s... more This work presents the analysis, design, and implementation of an efficient and wideband active-split dual-feed distributed amplifier (AS-DFDA) in 0.13µm CMOS technology. It consists of a dualfeed (DF) output stage with a passive combiner and an active-split (AS) input stage. The dual-feed stage is used to enhance the gain and output power of the proposed AS-DFDA by utilising both the forward and reverse gains of a conventional distributed topology. The DF stage requires an in-phase equi-amplitude signals feeding the DF gate lines from both sides which is accomplished by an active-split stage based on the split drain-line topology providing a wideband input match along with the extra leaverage in gain. An external capacitance in series with the DF stage devices is deployed to increase the cutoff frequency of the dual-feed gate lines. Further, the interstage lines are terminated with idle-line terminations on both ends to target flat gain. The amplified signal from DF stage is combined through an output impedance matched direct passive combiner. The measured results show a 13-10 dB gain from 4-22 GHz and output return loss of 6dB over the entire bandwidth. The measured output saturated power, P SAT , of 10.6 dBm with peak power added efficiency (PAE) of 15.1% is acheived at 5 GHz while a minimum peak PAE of 9% is obtained over the entire bandwidth. The AS-DFDA has a noise figure of 4-6 dB and occupies an active area of only 0.45 mm 2 , respectively.

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering ... more Serietitel och serienummer Title of series, numbering ISSN-Titel Title Design och implementering av en asymmetrisk Doherty Effekt Förstärkare er på 2,65 GHz i GaN HEMT teknik Design and Implementation of an Asymmetric Doherty Power Amplifier at 2.

Efficient amplification of signals with high PAPR using a novel multilevel LINC transmitter architecture

2012 42nd European Microwave Conference, 2012

ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter a... more ABSTRACT This paper presents a novel energy-efficient multistandard multilevel LINC transmitter architecture. The proposed system is able to provide a large number of reconfigurable multiple levels by arbitrarily controlling the output power of the two efficient power amplifiers. The novelty of the architecture relies in the efficient generation of the arbitrary multilevels. In fact, the system uses only one fixed supply voltage. An algorithm is developed to optimise the different symmetrical levels depending on the actual signal statistics in order to boost average system efficiency. A multilevel LINC transmitter system demonstrator was build to validate the proposed concept. Besides The system employs two identical hybrid power amplifiers designed using GaN HEMTs for a centre frequency of 2.28 GHz and output power of 40 dBm, the system employs only off-the-shelf components or measurement equipment. Measurement results on the demonstrator show that compared with a conventional LINC transmitter, average power efficiency of the proposed system can be improved from 28 % to 41 % for a WCDMA signal with a measured adjacent-channel-power ratio (ACPR) below -45 dBc. For a 10 MHz LTE signal efficiency is improved by nearly 24 percentage-points compared with a regular LINC system.

Efficient and wideband CMOS distributed power amplifiers for various high data rate applications

Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

2017 IEEE MTT-S International Microwave Symposium (IMS), 2017

This work presents the design and implementation of a flat-gain, efficient and wideband stacked d... more This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 −16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm2.

A −115 dBc/Hz Integrated Optoelectronic Oscillator in a BiCMOS Silicon Photonic Technology

2021 IEEE MTT-S International Microwave Symposium (IMS), 2021

An optoelectronic oscillator implemented in a 250 nm SiGe BiCMOS Silicon photonic technology is p... more An optoelectronic oscillator implemented in a 250 nm SiGe BiCMOS Silicon photonic technology is presented. It features a monolithic integration of the electronic amplifier components, the electro-optical modulator and the photodiode to achieve a low-parasitics and compact solution on a single chip. A phase noise of −115 dBc/Hz at a frequency offset of 100 kHz from the fundamental frequency of 750 MHz was measured. The phase noise is among the lowest for monolithically integrated optoelectronic oscillators. The frequency response gives a promising outlook to future fully monolithic integrated optoelectronic oscillators when a low loss micro-resonator is utilized to simultaneously act as an optical delay element and filter at frequencies above 20 GHz.

Analog Integrated Circuits and Signal Processing, 2016

This work presents the design and implementation of a fully integrated and compact broadband medi... more This work presents the design and implementation of a fully integrated and compact broadband medium stacked power amplifier in standard 65 nm bulk CMOS. The amplifier topology utilizes three NMOS stack and three PMOS stack at the output to primarily increase the output impedance along with the output voltage swing. The load impedance is further optimized with a resistive feedback to the input active device which not only results in broadband operation but also helps in avoiding large and lossy broadband output matching network, resulting in a significant area reduction. Further, small interstage peaking inductors are employed to peak the parasitics capacitances that limit the broadband operation. The proposed amplifier works directly into a 50X load and shows a measured peak saturated output power from 13 to 8.5 dBm and a P 1dB of 7-4 dBm from 0.3 to 10 GHz. The drain and peak power added efficiency are 6.5 and 4.3 % under 4 V supply with DC power consumption of 160 mW. The measured small signal gain is around 9 dB with a gain ripple of ±1.5 dB till 7 GHz and 5.4 dB at 10 GHz, yielding a fractional bandwidth of 188 %. The measured load-pull-1 dB,-2 dB output power contours verify the optimum impedance around 50 X. The active chip area is only 0.44 mm 2 .

IEEE Transactions on Microwave Theory and Techniques, 2017

This paper presents the design and implementation of efficient and wideband stacked distributed p... more This paper presents the design and implementation of efficient and wideband stacked distributed power amplifiers (SDPAs) in 0.13-µm CMOS technology. To obtain high output swing along with reasonable gain, a four-transistor stack is utilized. Voltage alignment at the drain of each device in the stack is obtained by allowing a small ac swing at the gate due to voltage division between the gate-source capacitance, C gs , and the external gate capacitance. Interstage matching is performed by peaking inductors. Further, the four-transistor stack has been replicated in four sections in a distributed topology to obtain wideband operation. A uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines. Based on the said approach, two topologies, the SDPA and the stackedcascode distributed power amplifier (SCDPA), are designed, implemented, and compared in terms of their performance. For SDPA, measured results show at least 10 ± 0.3 dB of small-signal gain from 2 to 16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with a peak efficiency of 17% and an OIP3 of 22 dBm. The SCDPA shows a measured small-signal gain of more than 10 dB at low frequencies and drops to 10 dB at 10 GHz. Also, the SCDPA demonstrates a saturated output power of 19.8 dBm with a peak efficiency of 19% and an OIP3 of 23 dBm. Both power amplifiers occupy an area of 0.83 mm 2 .

Analysis and design of class-O RF power amplifiers for wireless communication systems

Analog Integrated Circuits and Signal Processing, 2016

In this paper, we present analysis, design and show experimental results of a new type of CMOS ba... more In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are common-source (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P$$_{1\,{\mathrm{dB}}}$$1dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 \%$$% is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than −30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 \%$$%. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.

Design and implementation of an electrical interface for ring modulators using CPWs

This work presents the design and implementation of an electrical interface using coplanar wavegu... more This work presents the design and implementation of an electrical interface using coplanar waveguides (CPWs) to drive high speed ring modulators. To show this, first a small-signal model (SSM) of the modulator is developed by measuring its S11 response. The SSM is simulated with a conventional CPW to highlight the reflection problem emerging from the mismatch between the 50 Omega system reference and the high input impedance of the ring modulator which is around 1kOmega. The mismatch problem is mitigated by the proposed five-pin CPW design with ground-signalground- signal-ground (GSGSG) structure which terminates the reflection into an external 50 Omega termination. The proposed CPW demonstrates a measured S11 magnitude response below -15 dB throughout the frequency range of 25 GHz and -10 dB until 40 GHz.