Francois Roy - Academia.edu (original) (raw)

Papers by Francois Roy

IEEE Transactions on Nuclear Science, 2012

OATAO is an open access repository that collects the work of Toulouse researchers and makes it fr... more OATAO is an open access repository that collects the work of Toulouse researchers and makes it freely available over the web where possible.

We demonstrate a back illuminated colour image sensor with a 1.4µm pixel pitch. A novel backside ... more We demonstrate a back illuminated colour image sensor with a 1.4µm pixel pitch. A novel backside adapted pinned deep diode on n-substrates has been developed and characterized in order to achieve an improved colour separation. High quantum efficiency around 60% in the visible light spectrum has been attained whereas the other parameters stay in line with standard front side illuminated image sensors. Introduction: Backside illuminated (BSI) CMOS image sensors have been reported as a possible solution for the 1.4µm pixel pitch and below [1]. Beside the multiple advantages, like 100% fill factor, lower optical stack and higher metal packaging density [2-4], the BSI sensors also point out several design and process challenges, like the backside to frontside alignment and the electrical crosstalk [3-4]. We have realized a colorized BSI CMOS image sensor demonstrator with a 1.4µm pixel pitch in 1T5 architecture and a deep pinned photodiode on n-substrates for effective interpixel junctio...

A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pi... more A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pinned photodiode is investigated. The proof of a vertical pinning is made thanks to a study of the maximum diode depletion potential for different diode widths. Diode doping strategy is described in order to optimize in-depth charge storage. Simulation results show good matching when compared to scanning capacitance microscopy (SCM). A new silicon on insulator (SOI) wafer with embedded ONO broadband antireflective coating (ARC) fabrication technique is presented and demonstrates further improvement in terms of quantum efficiency (QE), with 63% in green spectrum. Process solutions such as additional thermal treatment are provided to control maximum diode depletion potential. A transfer gate (TG) is stacked above the photodiode and its according charge transfer technique is investigated. Pixel performances show full-well capacity of more than 11000 electrons.

2017 2nd International Conference on Image, Vision and Computing (ICIVC), 2017

We present our studies on small-sized pixel structures for high-resolution CMOS image sensors. To... more We present our studies on small-sized pixel structures for high-resolution CMOS image sensors. To minimize the number of pixel components, single-transistor pixel and 2T pixel architecture were proposed. To deal with crosstalk between pixels, MOS capacitor deep trench isolation (CDTI) was integrated. CDTI-integrated pixel allows better achievements in dark current and full-well capacity in comparison with the configuration integrating oxide-filled deep trench isolation (DTI). To improve quantum efficiency (QE) and minimize optical crosstalk, back-side illumination (BSI) was developed. Also, vertical photodiode was proposed to maximize its charge-collection region. To take advantages of these structures/technologies, we developed two pixel options (P-type and N-type) combining CDTI or DTI, BSI and vertical photodiode. All the presented pixel structures were designed in 1.4µm-pitch sensor arrays, fabricated and tested.

Sensors, 2020

Tackling issues of implantation-caused defects and contamination, this paper presents a new compl... more Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

IEEE Electron Device Letters, 2018

2008 IEEE International Electron Devices Meeting, 2008

This session is devoted to imaging technologies and focuses on new materials, sensor architecture... more This session is devoted to imaging technologies and focuses on new materials, sensor architectures trend and new applications. The first paper describes large format CCD for professional applications. The next paper introduces image sensor using CuInGaSe2 for wider spectral range. The third paper presents a 3D architecture back illuminated sensor. The invited paper describes technology trends in order to realize smaller CIS pixel size toward 1.0µm. The next paper present a biosensor capable of wireless operation and low light detection. To conclude, the last one introduces the flexible terahertz material showing a potential and next step to construct a functional THz cloak.

Charge-Coupled Devices and Solid State Optical Sensors, 1990

A 2/3-inch format 768(H) x 576 (V) pixel CCD image sensor has been developed, fabricated and test... more A 2/3-inch format 768(H) x 576 (V) pixel CCD image sensor has been developed, fabricated and tested. It has a frame transfer organization and is incorporating a lateral built in anti-blooming system. A horizontal resolution of more than 500 TV lines has been obtained and photosensitivity reaches 30 mv/lux. By the possible use of two video outputs, an image mirror function is provided. Thanks to its windowing device, the sensor is well suited for tracking applications.

IEEE Transactions on Nuclear Science, 2012

pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradia... more pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradiated with source. The HPD sensors exhibit much lower dark current degradation than equivalent commercial sensors using an Electron collection Pinned Photodiode (EPD). This hardness improvement is mainly attributed to carrier accumulation near the interfaces induced by the generated positive charges in dielectrics. The pre-eminence of this image sensor based on hole collection pinned photodiode architectures in ionizing environments is demonstrated. Index Terms-Active pixel sensors, APS, CIS, CMOS 4T image sensor, CMOS image sensors, dark current, hole collection pinned photodiode, hole-based detector, pinned photodiode.

IEEE Transactions on Nuclear Science, 2012

OATAO is an open access repository that collects the work of Toulouse researchers and makes it fr... more OATAO is an open access repository that collects the work of Toulouse researchers and makes it freely available over the web where possible.

We demonstrate a back illuminated colour image sensor with a 1.4µm pixel pitch. A novel backside ... more We demonstrate a back illuminated colour image sensor with a 1.4µm pixel pitch. A novel backside adapted pinned deep diode on n-substrates has been developed and characterized in order to achieve an improved colour separation. High quantum efficiency around 60% in the visible light spectrum has been attained whereas the other parameters stay in line with standard front side illuminated image sensors. Introduction: Backside illuminated (BSI) CMOS image sensors have been reported as a possible solution for the 1.4µm pixel pitch and below [1]. Beside the multiple advantages, like 100% fill factor, lower optical stack and higher metal packaging density [2-4], the BSI sensors also point out several design and process challenges, like the backside to frontside alignment and the electrical crosstalk [3-4]. We have realized a colorized BSI CMOS image sensor demonstrator with a 1.4µm pixel pitch in 1T5 architecture and a deep pinned photodiode on n-substrates for effective interpixel junctio...

A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pi... more A novel 1.4µm pitch pixel architecture dedicated for backside process with embedded vertically pinned photodiode is investigated. The proof of a vertical pinning is made thanks to a study of the maximum diode depletion potential for different diode widths. Diode doping strategy is described in order to optimize in-depth charge storage. Simulation results show good matching when compared to scanning capacitance microscopy (SCM). A new silicon on insulator (SOI) wafer with embedded ONO broadband antireflective coating (ARC) fabrication technique is presented and demonstrates further improvement in terms of quantum efficiency (QE), with 63% in green spectrum. Process solutions such as additional thermal treatment are provided to control maximum diode depletion potential. A transfer gate (TG) is stacked above the photodiode and its according charge transfer technique is investigated. Pixel performances show full-well capacity of more than 11000 electrons.

2017 2nd International Conference on Image, Vision and Computing (ICIVC), 2017

We present our studies on small-sized pixel structures for high-resolution CMOS image sensors. To... more We present our studies on small-sized pixel structures for high-resolution CMOS image sensors. To minimize the number of pixel components, single-transistor pixel and 2T pixel architecture were proposed. To deal with crosstalk between pixels, MOS capacitor deep trench isolation (CDTI) was integrated. CDTI-integrated pixel allows better achievements in dark current and full-well capacity in comparison with the configuration integrating oxide-filled deep trench isolation (DTI). To improve quantum efficiency (QE) and minimize optical crosstalk, back-side illumination (BSI) was developed. Also, vertical photodiode was proposed to maximize its charge-collection region. To take advantages of these structures/technologies, we developed two pixel options (P-type and N-type) combining CDTI or DTI, BSI and vertical photodiode. All the presented pixel structures were designed in 1.4µm-pitch sensor arrays, fabricated and tested.

Sensors, 2020

Tackling issues of implantation-caused defects and contamination, this paper presents a new compl... more Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

IEEE Electron Device Letters, 2018

2008 IEEE International Electron Devices Meeting, 2008

This session is devoted to imaging technologies and focuses on new materials, sensor architecture... more This session is devoted to imaging technologies and focuses on new materials, sensor architectures trend and new applications. The first paper describes large format CCD for professional applications. The next paper introduces image sensor using CuInGaSe2 for wider spectral range. The third paper presents a 3D architecture back illuminated sensor. The invited paper describes technology trends in order to realize smaller CIS pixel size toward 1.0µm. The next paper present a biosensor capable of wireless operation and low light detection. To conclude, the last one introduces the flexible terahertz material showing a potential and next step to construct a functional THz cloak.

Charge-Coupled Devices and Solid State Optical Sensors, 1990

A 2/3-inch format 768(H) x 576 (V) pixel CCD image sensor has been developed, fabricated and test... more A 2/3-inch format 768(H) x 576 (V) pixel CCD image sensor has been developed, fabricated and tested. It has a frame transfer organization and is incorporating a lateral built in anti-blooming system. A horizontal resolution of more than 500 TV lines has been obtained and photosensitivity reaches 30 mv/lux. By the possible use of two video outputs, an image mirror function is provided. Thanks to its windowing device, the sensor is well suited for tracking applications.

IEEE Transactions on Nuclear Science, 2012

pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradia... more pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradiated with source. The HPD sensors exhibit much lower dark current degradation than equivalent commercial sensors using an Electron collection Pinned Photodiode (EPD). This hardness improvement is mainly attributed to carrier accumulation near the interfaces induced by the generated positive charges in dielectrics. The pre-eminence of this image sensor based on hole collection pinned photodiode architectures in ionizing environments is demonstrated. Index Terms-Active pixel sensors, APS, CIS, CMOS 4T image sensor, CMOS image sensors, dark current, hole collection pinned photodiode, hole-based detector, pinned photodiode.