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Papers by Gilberto Ochoa-Ruiz

Research paper thumbnail of A high-level methodology for automatically generating dynamically reconfigurable systems using IP-XACT and the UML MARTE profile

Http Www Theses Fr, Nov 14, 2013

Research paper thumbnail of Dynamic partial reconfiguration and video distribution in a reconfigurable device

Research paper thumbnail of An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems

ACM Transactions on Design Automation of Electronic Systems, 2015

Research paper thumbnail of Análisis y simulación del modelo físico de un invernadero bajo condiciones climáticas de la región central de México

Research paper thumbnail of Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015

Research paper thumbnail of Accelerating Partial Bitstream Relocation in Highly-Scalable DPR Applications

Research paper thumbnail of Performance comparison of two hardware implementations of the deblocking filter used in H.264 by changing the utilized data width

International Workshop on Systems, Signal Processing and their Applications, WOSSPA, 2011

Research paper thumbnail of Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 2012

Research paper thumbnail of High-level modelling and automatic generation of dynamicaly reconfigurable systems

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase... more Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification,

Research paper thumbnail of Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study

2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Research paper thumbnail of Model-Driven Approach for Automatic Dynamic Partially Reconfigurable IP Customization

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Research paper thumbnail of A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

2013 International Conference on Control, Decision and Information Technologies (CoDIT), 2013

ABSTRACT Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to ov... more ABSTRACT Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time overhead might proof prohibitive. In order to find the best compromise between these approaches, we make use of the OORBIT tool (Offline/Online Relocation of Bitstreams) which helps us to accelerate the PBR considerably. In this paper, we compare the developed tool to others in previous works, specifically in the context of many-core applications; we give a particular importance to the reduction in the relocation time, which must to increase the time overhead already incurred by using partial reconfiguration. In this paper, we show how the tool has been used in this context, and a comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation process more amenable.

Research paper thumbnail of A digital watermarking algorithm based on quantization of the DCT: Application on medical imaging

2013 International Conference on Control, Decision and Information Technologies (CoDIT), 2013

ABSTRACT The objective of this paper is to elaborate a new watermarking algorithm applied to the ... more ABSTRACT The objective of this paper is to elaborate a new watermarking algorithm applied to the medical imaging. This algorithm must be invisible, robust and has a rate, relatively high, integrating data. The proposed method uses the standard JPEG compression for the integration of medical data. The insertion block is inserted just after the quantization phase. To control identification and eventually the correction (if possible) of the inserted data, we use a series of turbocodes to recover the inserted data, after application of several attacks. The simulation studies are applied on MRI medicals images.

Research paper thumbnail of A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Microprocessors and Microsystems, 2013

ABSTRACT Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary task... more ABSTRACT Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the best compromise between these approaches, we have developed the OORBIT tool (Offline/Online Relocation of Bitstreams) which accelerates the relocation time considerably. The methodology consists, firstly, in an offline bitstream modification phase which generates relocatable bitstreams including additional relocation data. Afterwards, online relocation is performed by a simple substitution of the initial location data by those calculated offline, corresponding to the target PRR. In this paper, we provide a detailed description of our methodology, emphasizing its interaction with the newest Xilinx Partition PR Design Flow, which results in major changes compared to previous efforts. Finally, a performance comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation more amenable.

Research paper thumbnail of IP-XACT and marte based approach for partially reconfigurable systems-on-chip

Research paper thumbnail of An object-oriented architecture for sensorless cutting force feedback for CNC milling process monitoring and control

Advances in Engineering Software, 2010

Research paper thumbnail of A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Design Automation for Embedded Systems, 2012

Research paper thumbnail of A high-level methodology for automatically generating dynamically reconfigurable systems using IP-XACT and the UML MARTE profile

Http Www Theses Fr, Nov 14, 2013

Research paper thumbnail of Dynamic partial reconfiguration and video distribution in a reconfigurable device

Research paper thumbnail of An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems

ACM Transactions on Design Automation of Electronic Systems, 2015

Research paper thumbnail of Análisis y simulación del modelo físico de un invernadero bajo condiciones climáticas de la región central de México

Research paper thumbnail of Kaolin: A system-level AADL tool for FPGA design reuse, upgrade and migration

2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2015

Research paper thumbnail of Accelerating Partial Bitstream Relocation in Highly-Scalable DPR Applications

Research paper thumbnail of Performance comparison of two hardware implementations of the deblocking filter used in H.264 by changing the utilized data width

International Workshop on Systems, Signal Processing and their Applications, WOSSPA, 2011

Research paper thumbnail of Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 2012

Research paper thumbnail of High-level modelling and automatic generation of dynamicaly reconfigurable systems

Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), 2011

Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase... more Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification,

Research paper thumbnail of Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study

2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Research paper thumbnail of Model-Driven Approach for Automatic Dynamic Partially Reconfigurable IP Customization

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Research paper thumbnail of A Novel approach for accelerating bitstream relocation in many-core partially reconfigurable applications

2013 International Conference on Control, Decision and Information Technologies (CoDIT), 2013

ABSTRACT Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to ov... more ABSTRACT Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time overhead might proof prohibitive. In order to find the best compromise between these approaches, we make use of the OORBIT tool (Offline/Online Relocation of Bitstreams) which helps us to accelerate the PBR considerably. In this paper, we compare the developed tool to others in previous works, specifically in the context of many-core applications; we give a particular importance to the reduction in the relocation time, which must to increase the time overhead already incurred by using partial reconfiguration. In this paper, we show how the tool has been used in this context, and a comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation process more amenable.

Research paper thumbnail of A digital watermarking algorithm based on quantization of the DCT: Application on medical imaging

2013 International Conference on Control, Decision and Information Technologies (CoDIT), 2013

ABSTRACT The objective of this paper is to elaborate a new watermarking algorithm applied to the ... more ABSTRACT The objective of this paper is to elaborate a new watermarking algorithm applied to the medical imaging. This algorithm must be invisible, robust and has a rate, relatively high, integrating data. The proposed method uses the standard JPEG compression for the integration of medical data. The insertion block is inserted just after the quantization phase. To control identification and eventually the correction (if possible) of the inserted data, we use a series of turbocodes to recover the inserted data, after application of several attacks. The simulation studies are applied on MRI medicals images.

Research paper thumbnail of A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

Microprocessors and Microsystems, 2013

ABSTRACT Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary task... more ABSTRACT Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the best compromise between these approaches, we have developed the OORBIT tool (Offline/Online Relocation of Bitstreams) which accelerates the relocation time considerably. The methodology consists, firstly, in an offline bitstream modification phase which generates relocatable bitstreams including additional relocation data. Afterwards, online relocation is performed by a simple substitution of the initial location data by those calculated offline, corresponding to the target PRR. In this paper, we provide a detailed description of our methodology, emphasizing its interaction with the newest Xilinx Partition PR Design Flow, which results in major changes compared to previous efforts. Finally, a performance comparative analysis is detailed to highlight the significant relocation speedups that might help in making the relocation more amenable.

Research paper thumbnail of IP-XACT and marte based approach for partially reconfigurable systems-on-chip

Research paper thumbnail of An object-oriented architecture for sensorless cutting force feedback for CNC milling process monitoring and control

Advances in Engineering Software, 2010

Research paper thumbnail of A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile

Design Automation for Embedded Systems, 2012