Hans Kerkhoff - Academia.edu (original) (raw)

Papers by Hans Kerkhoff

A new direction in short-range wireless applications has appeared in the form of high-speed data ... more A new direction in short-range wireless applications has appeared in the form of high-speed data communication devices for distances of hundreds meters. Behind these embedded applications, a complex heterogeneous architecture is built. Moreover, these short range communications are introduced into critical applications, where the dependability/reliability is mandatory. Thus, dependability concerns around reliability evaluation become a major challenge in these systems, and pose several questions to answer. Obviously, in such systems, the attribute reliability has to be investigated for various components and at different abstraction levels. In this paper, we discuss the investigation of dependability in wireless short range systems. We present a hardware platform for wireless system dependability analysis as an alternative for the time consuming simulation techniques. The platform is built using several instances of one of the commercial FPGA platforms available on the market place. We describe the different steps of building the wireless hardware platform for short range systems dependability analysis. Then, we show how this HW platform based dependability investigation framework can be a very interactive approach. Based on this platform we introduce a new methodology and a flow to investigate the different parts of system dependability at different abstraction levels. The benefits to use the proposed framework are three fold: first, it takes care of the whole system (HW/SW-digital part, mixed RF part, and wireless part); Second, the hardware platform enables to explore the application's reliability under real environmental conditions taking into account the effect of the environment threats on the system; And last, the wireless platform built for dependability investigation present a fast investigation approach in comparison with the time consuming co-simulation technique.

Reconfigurable Computing, 2011

Abstract The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create... more Abstract The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create a highly scalable and dependable reconfigurable system concept for a wide range of tomorrow&amp;amp;amp;#x27;s streaming DSP applications. Within CRISP, a network-on-chip based many-...

Proceedings ED&TC European Design and Test Conference, 1996

The miniaturization of electronic systems in areas as electronic integration and electronic packa... more The miniaturization of electronic systems in areas as electronic integration and electronic packaging allows the inclusion of devices on reduced substrates constituting a MultiChip Module (MCM). However, with the miniaturization of microsystems big troubles appear in the testing of the MCM. In order to solve the MCM test problem, this paper analyses the cost of using test structures on MCM-Deposited active substrates. Cost results are obtained from yield calculations of test structures placed on active substrate.

Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 2002

Recent developments in the field of MEMS indicate a clear move toward systems, rather than just i... more Recent developments in the field of MEMS indicate a clear move toward systems, rather than just individual components. Design and fabrication of these components include new methods and techniques. Does testing require new methodologies and tools ? Will we be able to include MEMS in the SoCs flow ?

Storage and Retrieval for Image and Video Databases, 1999

ABSTRACT Microsystem testing has to cope with many problems, resulting from inaccessibility, diff... more ABSTRACT Microsystem testing has to cope with many problems, resulting from inaccessibility, different technologies and non-electrical failure modes. Possible test techniques have been investigated to test a new advanced microsystem. The implementation form and application area highly contributes to the choices made.

In this paper the implementation of the test strategy in a so-called Very Long Instruction Word T... more In this paper the implementation of the test strategy in a so-called Very Long Instruction Word Transport Triggered Architecture (VLIW-TTA) is discussed. The complete test strategy is derived referring to the results of test synthesis, carried out in the early phase of the design. It takes the area/throughput parameters into account. The test strategy, exploiting the regularity and modularity of the VLIW-TTA structure, remains general for an arbitrary application and instantiation of the TTA processor and is based on the partial scan approach along with the functional test. The test-time analysis, in order to justify our approach and show the superiority over the classical full-scan, has been performed. The results of our strategy are shown in a few examples at the end of the paper.

Proceedings 18th IEEE VLSI Test Symposium, 2000

Testing of high performance integrated circuits is becoming increasingly a challenging task owing... more Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to their limited high frequency capabilities. In this article we outline a Design-for-Test methodology such that high performance devices can be tested on relatively low performance testers. In addition, a BIST framework is discussed based on this methodology. Various implementation aspects of this technique are also addressed.

Proceedings IEEE European Test Workshop, 2000

0-7695-0701-8/00 $10.00 0 2000 IEEE

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988

A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS l... more A set of CAD tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based upon the cost-table method. The general circuit structure, the cost-table functions and the decomposition procedure used in the cost-table synthesis program are explained. The synthesis program is based upon a logically complete set of basic elements for CMCL circuits. After circuit synthesis the actual layout is generated using standard-cell IC design tools. 1 Introduction. K=1 Lro k=l 1=1 a=l b=l K=2 L=-1 k=l 111 a-1 b-0 K=1 L=-2 k=l l=l a=1 b-0 K=Z L=O k-1 111 a=l b=l K=l L=O k=2 1-1 a 4 b-1 K 4 L=-3 k=2 l=l a=l tro K=l L=-3 k-2 l=l a=l &o K-2 L=1 k=l 1=1 a=l b=l K=2 LEO k=2 111 a 4 b=l K=l L=-1 b 2 111 a=l b=l K=3 L=O k=l 1=1 a-2 b=l K=2 L=1 k=2 l=l a=l b=l K-2 L d k=3 111 a=l b=l K-1 L=O k=3 111 a-1 b=2 K=l L=-1 k=3 1 4 a-1 b-1 K=2 L=l k-2 l=l a=l b=2 K=l L=-2 k=3 1-1 a=l bl K=l L 4 k=l l=l a-1 b-3 K=2 L=l k=3 1=1 a-1 b=2 K=l L=O k 4 1-1 a-1 b=3 K=2 L=-1 k=4 1-1 a=l b=l K=l L-1 k 4 111 a-1 b-2 K=2 L=2 k=3 l=l a 4 b=2 K=2 L=l k=4 1=1 a-1 b=2 K=1 LEO k=5 111 a-1 b-3 K=l L=-1 Its5 111 a-1 b-2 K=4 L=O k=1 111 a=3 b=2 K=2 L=1 k=5 1=1 vl b-2 K=5 L=-1 k=l 1 4 a=3 b=l K=2 L=3 k=5 l=l a-1 b-3

International Test Conference 1988 Proceeding@m_New Frontiers in Testing, 1988

In this paper a new method is presented to analyze the testability of both linear and nonlinear a... more In this paper a new method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm will find sets of inseparable parameters and determine whether it is possible to calculate a certain parameter with sufficient accuracy. It also determines a subset of appropriate measurements if redundant measurements are present.

Proceedings the European Design and Test Conference. ED&TC 1995, 1995

The few literature available on a combined approach is restricted to small, resetable synthesised... more The few literature available on a combined approach is restricted to small, resetable synthesised circuits, whereas in this paper a combined approach to test pattern generation for delay faults in general synchronous sequential circuits is presented. The presented system consists of a dedicated test pattern generator for delay faults in combinational blocks of sequential circuits, which is tightly coupled to a dedicated test pattern generator for static faults in sequential circuits that handles the sequential propagation and initialisation. This highly integrated approach results in effective test pattern generation for delay faults, yet without losing the guarantee to completeness.

[1989] Proceedings of the 1st European Test Conference, 1989

Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's, 1991

Proceedings First Asian Test Symposium (ATS `92), 1992

ABSTRACT An efficient parallel pattern multiple-fault propagation (MFP) technique for the single ... more ABSTRACT An efficient parallel pattern multiple-fault propagation (MFP) technique for the single stuck-at fault simulation in combinational circuits is presented. This technique is able to operate in conjunction with several existing fault simulation techniques, such as the parallel-pattern simulation and the fanout-free region concept. Experimental results have shown significant improvements in the simulation speed over the existing approaches. The fault simulator described adopts different simulation algorithms at different simulation stages to optimize the simulator performance

Physical review. A, Jan 15, 1989

... from the high-energy toroidal grating monochromator(HE-TGM l) be-tween 270 and 1000 eV. The p... more ... from the high-energy toroidal grating monochromator(HE-TGM l) be-tween 270 and 1000 eV. The photoemission measure-ments covering the intermediate energy range from 40 to 170 eV took place at the TGMof HASYLAB. ' We used the time-of-fiight (TOF) method for the ...

Physical review. A, 1986

Partial photoionization cross sections and angular-distribution asymmetry parameters were determi... more Partial photoionization cross sections and angular-distribution asymmetry parameters were determined for Kr 3d photoemission using photon energies of 100 to 280 eV (to 800 eV for the asymmetry parameter). For the 3p subshell, the branching ratio relative to the 3d cross section and the asymmetry parameter were measured using energies of 280 to 800 eV. These results show good agreement with Hartree-Fock-theory predictions at all photon energies. The summed intensity of 4p np satellites relative to the 3d main line was found to be approximately constant in the photon-energy range 180--280 eV, and the average asymmetry parameter for these shake-up states showed a marked increase over the same energy range.

ABSTRACT Reliability of electronic systems has been thoroughly investigated in literature and a n... more ABSTRACT Reliability of electronic systems has been thoroughly investigated in literature and a number of analytical approaches at the design stage are already available via examination of the circuit-level reliability effects based on device-level models. Reliability estimation during operational life of an electronic system still lacks a solution especially for analog and mixed signal systems. The current work will present a novel technique for indirectly estimating reliability during operational life of an electronic system. Reliability simulations during the design stage of a potential critical performance parameter, sensitive to aging effects, over a range of input-stress voltages and working-stress temperatures have been used to generate a set of degradation values per unit time. These values are then used at the system level to estimate the degradation in that particular performance parameter and hence system reliability by regularly monitoring the input-stress voltages and working-stress temperatures. The simulation results conducted for an example target system in a LabVIEW environment show that the proposed technique is viable.

Proceedings. 21st VLSI Test Symposium, 2003., 2003

The testable design and testing of a fully softwarecontrollable lab-on-a-chip, including a fluidi... more The testable design and testing of a fully softwarecontrollable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented.

International Test Conference, 2003. Proceedings. ITC 2003., 2003

Many of the semiconductor technologies are already temperature superconductor (HTS) technology [4... more Many of the semiconductor technologies are already temperature superconductor (HTS) technology [4]. facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconductor electronics (SCE) is capable of handling some of these high-end tasks. We have started a defect-oriented test methodology for SCE, so that reliable systems can be implemented in this technology. In this paper, the details of the study on the Rapid Single-Flux Quantum (RSFQ) process are presented. We present common defects in the SCE processes and corresponding test methodologies to detect them. The (measurement) results prove that we are able to detect possible random defects for statistical purposes in yield analysis. This paper also presents possible test methodologies for RSFQ circuits based on defect oriented testing (DOT).