Hussain AlAsaad - Academia.edu (original) (raw)

Uploads

Papers by Hussain AlAsaad

Esa, 2004

This paper introduces two new methods for observing and recording the vectors that have been asse... more This paper introduces two new methods for observing and recording the vectors that have been asserted on a bus. The first is a software approach that uses a novel data structure similar to binary decision diagrams which allows for a compact representation of stored values. Even though the new data structure presented in this paper can potentially grow to contain just as many nodes as there are possible values, such cases are often rare. The second is a hardware approach that is based on a simple circuit consisting of a small memory and two counters and has the ability to perform at the speed of the microprocessor.

Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors

A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm... more A new fault tolerant multipipeline array architecture and its diagnosis/reconfiguration algorithm will be presented. This multipipeline array design methodology is characterized by constant, fault distribution independent interstage path lengths. Other features include a low hardware overhead and a high survival rate when it is compared to existing approaches.

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940), 2004

In this paper we present a preliminary method of validating a high-level microprocessor implement... more In this paper we present a preliminary method of validating a high-level microprocessor implementation by generating a test sequence for a collection of abstract design error models that can be used to compare the responses of the implementation against the specification. We first introduce a general description of the abstract mutation-based design error models that can be tailored to span any coverage measure for microprocessor validation. Then we present the clusteringand-partitioning technique that single-handedly makes the concurrent design error simulation of a large set of design errors efficient and allows for the acquisition of statistical data on the distribution of design errors across the design space. We finally present a method of effectively using this statistical information to guide the ATPG efforts.

International Journal of Engineering and Technology, 2011

Synchronous logic design is the dominant main stream integrated circuit design methodology. Flip-... more Synchronous logic design is the dominant main stream integrated circuit design methodology. Flip-flops are an inherent building block in any synchronous design. Furthermore flip-flops constitute most of the load on the clock distribution and power networks, which are the main power consuming networks of a synchronous integrated circuit. We survey, design and simulate a superset of flip-flops designed for low power and high performance. We highlight the basic design features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics. Moreover, we propose a new flip-flop design. We go in depth into a finer granularity comparison of the lowest peak power surveyed flip-flops reported in the literature; we show the competitiveness of the new design and make our recommendations.

Seventh International Workshop on Microprocessor Test and Verification (MTV'06), 2006

Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microproc... more Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we need to enable MVP's ATPG to learn important details of the circuit under validation as a means to explore critical new circuit scenarios. In this paper, we present new profiling mechanisms that can exist either as a pre-processor that gathers circuit information prior to the circuit validation process, or as run-time entities that allow MVP to learn from its progressive experience.

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006

Low power flip-flops are crucial for the design of low-power digital systems. In this paper we de... more Low power flip-flops are crucial for the design of low-power digital systems. In this paper we delve into the details of flip-flop design and optimization for low power. We compare the lowest power flip-flops reported in the literature and introduce a new flip-flop that competes with them.

2007 IEEE International Symposium on Circuits and Systems, 2007

Low-power consumption has become a highly important concern for synchronous standard-cell design,... more Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techniques. Glitches are not functionally significant in synchronous designs, but they consume a lot of power. By reducing glitching activity, we can reduce the dominant term in the power consumption of CMOS digital circuits. In this paper, we present a new method to estimate the glitching activity for different circuit nodes. The method is robust and produces accurate glitch probability numbers early in the design cycle. It does not have much overhead and it alleviates existing compute-intensive algorithms/methods. I.

2005 Sixth International Workshop on Microprocessor Test and Verification, 2005

Our mutation based validation paradigm (MVP) is a validation environment for high-level microproc... more Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architectural states (prospect states) that can possibly satisfy a set of constraints during MVP's test generation, we need to reduce the search space in the analysis process as early as possible. In this paper, we present some optimizations in the search space that speed up the overall test generation process.

Tenth IEEE International High-Level Design Validation and Test Workshop, 2005.

Proceedings AUTOTESTCON 2004.

A high-level concurrent design error simulator that can handle various design error/fault models ... more A high-level concurrent design error simulator that can handle various design error/fault models is presented. The simulator is a vital building block of a new promising method of high-level testing and design validation that aims at explicit design error/fault modeling, design error simulation, and modeldirected test pattern generation. We first describe how signals are represented in our concurrent fault simulation and the method of performing operations on these signals. We then describe how to handle the challenges in executing conditional statements when the signals used by the statements are augmented by an error/fault list. We further describe the method in which the error models are embedded into the simulator such that the result of a concurrent simulation matches that of a sequence of HDL simulations with the set of errors/faults inserted manually one by one. We finally demonstrate the application of our concurrent design error simulator on a typical Motorola microprocessor. Our simulator was able to detect all detectable and modeled design errors/faults for a given test sequence and was able to reveal valuable information about the behavior of erroneous designs.

Microprocessors are becoming increasingly complex and difficult to debug. Researchers are constan... more Microprocessors are becoming increasingly complex and difficult to debug. Researchers are constantly looking for new methods to increase the observability and controllability of microprocessors. This paper introduces a new method to improve the observability of modern microprocessors and thus simplifying the task of debugging them. The method revolves around an observation circuit that provides access to important internal signals without interrupting the microprocessor execution. The output of the observation circuit is ported to the output of the microprocessor in order to easily detect various physical faults and design errors. Experimental results show that physical faults and design errors are detected faster using our method. Moreover, several errors are detected by the observation circuit without being detected by the microprocessor outputs.

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008