Johannes Schemmel - Academia.edu (original) (raw)
Papers by Johannes Schemmel
Biological Cybernetics, 2011
In this paper we present a methodological framework that meets novel requirements emerging from u... more In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromor-
Frontiers in Neuroscience, 2011
Hardware implementations of spiking neurons can be extremely useful for a large variety of applic... more Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.
Edge detection is a common first step in artificial vision systems. Usually this task is performe... more Edge detection is a common first step in artificial vision systems. Usually this task is performed by computation on digitized data from an analog CCD or CMOS camera. This paper describes an analog approach to edge detection using a kind of resistive fuse algorithm. 66 × 66 pixels are interconnected with their nearest neighbors by a novel combination of switched
International Conference on Computers for People with Special Needs, 2000
We have built and operated a tactile vision substitution system based on 48 piezoelectric actuato... more We have built and operated a tactile vision substitution system based on 48 piezoelectric actuators assembled in a movable tactile output unit. The unit can be positioned at any location on a two dimensional surface to explore the line structure of a virtual image. This virtual tactile display (VTD) receives data either from camera systems equipped with suitable image processing
We present a new concept for multi-compartment emulation on neuromorphic hardware based on the Br... more We present a new concept for multi-compartment emulation on neuromorphic hardware based on the BrainScaleS wafer-scale system. The implementation features complex dendrite routing capabilities, realistic scaling of compartmental parameters and active spike propagation. Simulations proof the circuit’s capability of reproducing passive dendritic properties of a model from literature.
This paper surveys the research on intrinsic evolution of analog electronic circuits done at the ... more This paper surveys the research on intrinsic evolution of analog electronic circuits done at the University of Heidelberg. The aims of the project are discussed with reference to the related fields of evolvable hardware and analog design automation. A Field Programmable Transistor Array (FPTA) is used as the substrate for the artificial evolution process. It consists of 16 × 16 transistor cells fabricated in a 0.6 µm CMOS process. Static as well as dynamic properties of the programmable transistor array are estimated by characterization measurements of the chip. The chip is embedded in an evolution system consisting of a PC running the evolutionary algorithm and a PCI card that connects the PC to the FPTA and provides the conversion between digital and analog signals. As case studies the quasi dc behavior of different logic gates as well as a Gaussian output characteristic are evolved.
A network simulation paradigm was devel- oped to be consistent with observations of the high- con... more A network simulation paradigm was devel- oped to be consistent with observations of the high- conductance state of layer IV cortical neurons in an awake brain in-vivo. Two classes of integrate-and-fire based neurons, pyramidal (with adaptation) and inhibitory, were modeled. Synapses were conductance based. The high- conductance state was induced by synaptic bombardment with 1000 excitatory and 250 inhibitory Poisson
With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable... more With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable of implementing brain-scale neural models in hardware, there is an emerging need to be able to integrate multi-system combinations of sensors and cortical processors over distributed, multisite configurations. If there were a standard, direct interface allowing large systems to communicate using native signalling, it would be possible to use heterogeneous resources efficiently according to their task suitability. We propose a UDP-based AER spiking interface that permits direct bidirectional spike communications over standard networks, and demonstrate a practical implementation with two large-scale neuromorphic systems, BrainScaleS and SpiNNaker. Internally, the interfaces at either end appear as interceptors which decode and encode spikes in a standardised AER address format onto UDP frames. The system is able to run a spiking neural network distributed over the two systems, in both a s...
Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004., 2004
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog conve... more The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Programmable Transistor Array (FPTA) is used as the analog substrate for testing the candidate solutions. The FPTA features 256 programmable transistors, whose channel geometry and routing can be configured to form a large variety of transistor level analog circuits. A series of experiments reveals that variations of the output voltage range influence evolution's success more severely than varying the amount of available electronic resources or the geometrical setup. Although a considerable number of runs yield converters with a nonlinearity of less than 1 bit, no DAC is found to maintain a nonlinearity of less than 0.5 bits under worst case conditions, as required for a true 6-bit resolution. While the evolved circuits work comparably well at different time scales as well as on different dice, they lack the ability to abstract from the analog voltage levels of the digital input signals. It is experimentally verified that this can be remedied by inserting digital buffers at the circuits' inputs.
First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), 2006
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group wi... more This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future.
Proceedings 2002 NASA/DoD Conference on Evolvable Hardware, 2002
In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPT... more In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPTA chip are presented. The experiments discussed are restricted to the evolution of specified target DC behaviors. In the first series of experiments the evolution of different logic gates, namely NAND, NOR, AND, OR and XOR, is studied. The success rates in evolving the different logic gates are compared to each other. Furthermore the influence of three different methods of presenting the test patterns to the chip is analyzed. In a second series of experiments the evolution of a Gaussian voltage transfer characteristic is tackled. Thereby the influence of the chip area available to the genetic algorithm is studied.
Lecture Notes in Computer Science, 2004
ABSTRACT This article summarizes two experiments utilizing building blocks to nd analog electroni... more ABSTRACT This article summarizes two experiments utilizing building blocks to nd analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 programmable tran-sistors whose channel geometry and routing can be con gured to form a large variety of transistor level analog circuits. The transistor cells are either of type PMOS or NMOS and are arranged in a checkerboard pat-tern. Two case studies focus on improving arti cial evolution by using a building block library of four digital gates consisting of a NOR, a NAND, a bu er and an inverter. The methodology is applied to the design of the more complex logic gates XOR and XNOR as well as to the evolution of circuits discriminating between square waves of di erent frequencies.
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
Modeling neural tissue is an important tool to investigate biological neural networks. Until rece... more Modeling neural tissue is an important tool to investigate biological neural networks. Until recently, most of this modeling has been done using numerical methods. In the European research project "FACETS" this computational approach is complemented by different kinds of neuromorphic systems. A special emphasis lies in the usability of these systems for neuroscience. To accomplish this goal an integrated software/hardware
Lecture Notes in Computer Science, 2005
ABSTRACT This work tackles the problem of synthesizing transferable and reusa- ble operational am... more ABSTRACT This work tackles the problem of synthesizing transferable and reusa- ble operational ampliers on a eld programmable transistor array: the Heidel- berg FPTA. A multi-objective evolutionary algorithm is developed, in order to be able to include various specications of an operational amplier into the process of circuit synthesis. Additionally, the presented algorithm is designed to preserve the diversity within the population troughout evolution and is therefore able to efciently explore the design space. Furthermore, the evolved circuits are proven to work on the chip as well as in simulation outside the FPTA. Schematics of good solutions are presented and their characteristics are compared to those of basic manually created reference designs.
2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541), 2004
This work presents a new VLSI model for biological neural systems, a unified research tool for ne... more This work presents a new VLSI model for biological neural systems, a unified research tool for neuro- as well as computer science. It allows construction of neural microcircuits close to the biological specimen while maintaining a speed several orders faster than real time. The synapse model includes an implementation of spike time dependent plasticity (STDP). Therefore, the VLSI system allows
Genetic and Evolutionary Computation Conference, 2002
Lecture Notes in Computer Science, 2001
Abstract. The usefulness of an arti cial analog neural network is closely bound to its trainabili... more Abstract. The usefulness of an arti cial analog neural network is closely bound to its trainability. This paper introduces a new analog neural net-work architecture using weights determined by a genetic algorithm. The rst VLSI implementation presented in this paper achieves 200 giga con-nections per second with 4096 synapses on less than 1 mm, silicon area. Since the training can
Lecture Notes in Computer Science, 2007
This paper presents configuration methods for an existing neuromorphic hardware and shows first e... more This paper presents configuration methods for an existing neuromorphic hardware and shows first experimental results. The utilized mixed-signal VLSI 1 device implements a highly accelerated network of integrate-and-fire neurons. We present a software framework, which provides the possibility to interface the hardware and explore it from the point of view of neuroscience. It allows to directly compare both spike times and membrane potentials which are emulated by the hardware or are computed by the software simulator NEST, respectively, from within a single software scope. Membrane potential and spike timing dependent plasticity measurements are shown which illustrate the capabilities of the software framework and document the functionality of the chip.
The 2006 IEEE International Joint Conference on Neural Network Proceedings, 2006
This paper describes an area-efficient mixed-signal implementation of synapse-based long term pla... more This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI 1 model of a spiking neural network. The artificial synapses are based on an implementation of spike time dependent plasticity (STDP). In the biological specimen, STDP is a mechanism acting locally in each synapse. The presented electronic implementation succeeds in maintaining this high level of parallelism and simultaneously achieves a synapse density of more than 9k synapses per mm 2 in a 180 nm technology. This allows the construction of neural micro-circuits close to the biological specimen while maintaining a speed several orders of magnitude faster than biological real time. The large acceleration factor enhances the possibilities to investigate key aspects of plasticity, e.g. by performing extensive parameter searches.
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
ABSTRACT In this paper we describe our approach towards highly configurable neuromorphic hardware... more ABSTRACT In this paper we describe our approach towards highly configurable neuromorphic hardware systems that serve as useful and flexible tools in modeling neuroscience. We utilize a mixed-signal VLSI model that implements a massively accelerated network of spiking neurons, and we describe a novel methodological framework that allows to exploit both the speed and the programmability of this device for the systematic and simulator-like exploration of cortical network architectures. We present a variety of experimental results that illustrate the functionality of our modeling platform, and we verify all hardware measurements with reference software simulations. Especially on the network level these comparison studies are unique in terms of the quantitative correspondence between the data. The presented hardware experiments include high-conductance states in hardware neurons and the application of synaptic depression and facilitation for self-adjusting network architectures.
Biological Cybernetics, 2011
In this paper we present a methodological framework that meets novel requirements emerging from u... more In this paper we present a methodological framework that meets novel requirements emerging from upcoming types of accelerated and highly configurable neuromor-
Frontiers in Neuroscience, 2011
Hardware implementations of spiking neurons can be extremely useful for a large variety of applic... more Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin-Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.
Edge detection is a common first step in artificial vision systems. Usually this task is performe... more Edge detection is a common first step in artificial vision systems. Usually this task is performed by computation on digitized data from an analog CCD or CMOS camera. This paper describes an analog approach to edge detection using a kind of resistive fuse algorithm. 66 × 66 pixels are interconnected with their nearest neighbors by a novel combination of switched
International Conference on Computers for People with Special Needs, 2000
We have built and operated a tactile vision substitution system based on 48 piezoelectric actuato... more We have built and operated a tactile vision substitution system based on 48 piezoelectric actuators assembled in a movable tactile output unit. The unit can be positioned at any location on a two dimensional surface to explore the line structure of a virtual image. This virtual tactile display (VTD) receives data either from camera systems equipped with suitable image processing
We present a new concept for multi-compartment emulation on neuromorphic hardware based on the Br... more We present a new concept for multi-compartment emulation on neuromorphic hardware based on the BrainScaleS wafer-scale system. The implementation features complex dendrite routing capabilities, realistic scaling of compartmental parameters and active spike propagation. Simulations proof the circuit’s capability of reproducing passive dendritic properties of a model from literature.
This paper surveys the research on intrinsic evolution of analog electronic circuits done at the ... more This paper surveys the research on intrinsic evolution of analog electronic circuits done at the University of Heidelberg. The aims of the project are discussed with reference to the related fields of evolvable hardware and analog design automation. A Field Programmable Transistor Array (FPTA) is used as the substrate for the artificial evolution process. It consists of 16 × 16 transistor cells fabricated in a 0.6 µm CMOS process. Static as well as dynamic properties of the programmable transistor array are estimated by characterization measurements of the chip. The chip is embedded in an evolution system consisting of a PC running the evolutionary algorithm and a PCI card that connects the PC to the FPTA and provides the conversion between digital and analog signals. As case studies the quasi dc behavior of different logic gates as well as a Gaussian output characteristic are evolved.
A network simulation paradigm was devel- oped to be consistent with observations of the high- con... more A network simulation paradigm was devel- oped to be consistent with observations of the high- conductance state of layer IV cortical neurons in an awake brain in-vivo. Two classes of integrate-and-fire based neurons, pyramidal (with adaptation) and inhibitory, were modeled. Synapses were conductance based. The high- conductance state was induced by synaptic bombardment with 1000 excitatory and 250 inhibitory Poisson
With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable... more With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable of implementing brain-scale neural models in hardware, there is an emerging need to be able to integrate multi-system combinations of sensors and cortical processors over distributed, multisite configurations. If there were a standard, direct interface allowing large systems to communicate using native signalling, it would be possible to use heterogeneous resources efficiently according to their task suitability. We propose a UDP-based AER spiking interface that permits direct bidirectional spike communications over standard networks, and demonstrate a practical implementation with two large-scale neuromorphic systems, BrainScaleS and SpiNNaker. Internally, the interfaces at either end appear as interceptors which decode and encode spikes in a standardised AER address format onto UDP frames. The system is able to run a spiking neural network distributed over the two systems, in both a s...
Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004., 2004
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog conve... more The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Programmable Transistor Array (FPTA) is used as the analog substrate for testing the candidate solutions. The FPTA features 256 programmable transistors, whose channel geometry and routing can be configured to form a large variety of transistor level analog circuits. A series of experiments reveals that variations of the output voltage range influence evolution's success more severely than varying the amount of available electronic resources or the geometrical setup. Although a considerable number of runs yield converters with a nonlinearity of less than 1 bit, no DAC is found to maintain a nonlinearity of less than 0.5 bits under worst case conditions, as required for a true 6-bit resolution. While the evolved circuits work comparably well at different time scales as well as on different dice, they lack the ability to abstract from the analog voltage levels of the digital input signals. It is experimentally verified that this can be remedied by inserting digital buffers at the circuits' inputs.
First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06), 2006
This paper gives an overview over the progress that has been made by the Heidelberg FPTA group wi... more This paper gives an overview over the progress that has been made by the Heidelberg FPTA group within the field of analog evolvable hardware. Achievements are the design of a CMOS configurable transistor array (FPTA), the development of evolutionary algorithms (EAs) for analog circuit synthesis and the implementation of a modular framework, which makes it possible to use various substrates and simulation models for evolution experiments. The improvement of the EA is shown by comparing the performance of three implementations in evolving comparators. Additionally, results, obtained from the FPTA for the evolution of oscillators from scratch, are presented as an example for the successful application of the multi-objective Turtle GA. Finally, it is shown that a simplified software model of the Heidelberg FPTA is suitable to assess the real hardware, indicated by the fact that both substrates perform equally well in finding good solutions for comparators. This work aims at creating a customizable, modular framework that facilitates research on the performance and evolvability of possible FPTA topologies in the future.
Proceedings 2002 NASA/DoD Conference on Evolvable Hardware, 2002
In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPT... more In this paper the results of a series of intrinsic hardware evolution experiments with a CMOS FPTA chip are presented. The experiments discussed are restricted to the evolution of specified target DC behaviors. In the first series of experiments the evolution of different logic gates, namely NAND, NOR, AND, OR and XOR, is studied. The success rates in evolving the different logic gates are compared to each other. Furthermore the influence of three different methods of presenting the test patterns to the chip is analyzed. In a second series of experiments the evolution of a Gaussian voltage transfer characteristic is tackled. Thereby the influence of the chip area available to the genetic algorithm is studied.
Lecture Notes in Computer Science, 2004
ABSTRACT This article summarizes two experiments utilizing building blocks to nd analog electroni... more ABSTRACT This article summarizes two experiments utilizing building blocks to nd analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 programmable tran-sistors whose channel geometry and routing can be con gured to form a large variety of transistor level analog circuits. The transistor cells are either of type PMOS or NMOS and are arranged in a checkerboard pat-tern. Two case studies focus on improving arti cial evolution by using a building block library of four digital gates consisting of a NOR, a NAND, a bu er and an inverter. The methodology is applied to the design of the more complex logic gates XOR and XNOR as well as to the evolution of circuits discriminating between square waves of di erent frequencies.
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
Modeling neural tissue is an important tool to investigate biological neural networks. Until rece... more Modeling neural tissue is an important tool to investigate biological neural networks. Until recently, most of this modeling has been done using numerical methods. In the European research project "FACETS" this computational approach is complemented by different kinds of neuromorphic systems. A special emphasis lies in the usability of these systems for neuroscience. To accomplish this goal an integrated software/hardware
Lecture Notes in Computer Science, 2005
ABSTRACT This work tackles the problem of synthesizing transferable and reusa- ble operational am... more ABSTRACT This work tackles the problem of synthesizing transferable and reusa- ble operational ampliers on a eld programmable transistor array: the Heidel- berg FPTA. A multi-objective evolutionary algorithm is developed, in order to be able to include various specications of an operational amplier into the process of circuit synthesis. Additionally, the presented algorithm is designed to preserve the diversity within the population troughout evolution and is therefore able to efciently explore the design space. Furthermore, the evolved circuits are proven to work on the chip as well as in simulation outside the FPTA. Schematics of good solutions are presented and their characteristics are compared to those of basic manually created reference designs.
2004 IEEE International Joint Conference on Neural Networks (IEEE Cat. No.04CH37541), 2004
This work presents a new VLSI model for biological neural systems, a unified research tool for ne... more This work presents a new VLSI model for biological neural systems, a unified research tool for neuro- as well as computer science. It allows construction of neural microcircuits close to the biological specimen while maintaining a speed several orders faster than real time. The synapse model includes an implementation of spike time dependent plasticity (STDP). Therefore, the VLSI system allows
Genetic and Evolutionary Computation Conference, 2002
Lecture Notes in Computer Science, 2001
Abstract. The usefulness of an arti cial analog neural network is closely bound to its trainabili... more Abstract. The usefulness of an arti cial analog neural network is closely bound to its trainability. This paper introduces a new analog neural net-work architecture using weights determined by a genetic algorithm. The rst VLSI implementation presented in this paper achieves 200 giga con-nections per second with 4096 synapses on less than 1 mm, silicon area. Since the training can
Lecture Notes in Computer Science, 2007
This paper presents configuration methods for an existing neuromorphic hardware and shows first e... more This paper presents configuration methods for an existing neuromorphic hardware and shows first experimental results. The utilized mixed-signal VLSI 1 device implements a highly accelerated network of integrate-and-fire neurons. We present a software framework, which provides the possibility to interface the hardware and explore it from the point of view of neuroscience. It allows to directly compare both spike times and membrane potentials which are emulated by the hardware or are computed by the software simulator NEST, respectively, from within a single software scope. Membrane potential and spike timing dependent plasticity measurements are shown which illustrate the capabilities of the software framework and document the functionality of the chip.
The 2006 IEEE International Joint Conference on Neural Network Proceedings, 2006
This paper describes an area-efficient mixed-signal implementation of synapse-based long term pla... more This paper describes an area-efficient mixed-signal implementation of synapse-based long term plasticity realized in a VLSI 1 model of a spiking neural network. The artificial synapses are based on an implementation of spike time dependent plasticity (STDP). In the biological specimen, STDP is a mechanism acting locally in each synapse. The presented electronic implementation succeeds in maintaining this high level of parallelism and simultaneously achieves a synapse density of more than 9k synapses per mm 2 in a 180 nm technology. This allows the construction of neural micro-circuits close to the biological specimen while maintaining a speed several orders of magnitude faster than biological real time. The large acceleration factor enhances the possibilities to investigate key aspects of plasticity, e.g. by performing extensive parameter searches.
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010
ABSTRACT In this paper we describe our approach towards highly configurable neuromorphic hardware... more ABSTRACT In this paper we describe our approach towards highly configurable neuromorphic hardware systems that serve as useful and flexible tools in modeling neuroscience. We utilize a mixed-signal VLSI model that implements a massively accelerated network of spiking neurons, and we describe a novel methodological framework that allows to exploit both the speed and the programmability of this device for the systematic and simulator-like exploration of cortical network architectures. We present a variety of experimental results that illustrate the functionality of our modeling platform, and we verify all hardware measurements with reference software simulations. Especially on the network level these comparison studies are unique in terms of the quantitative correspondence between the data. The presented hardware experiments include high-conductance states in hardware neurons and the application of synaptic depression and facilitation for self-adjusting network architectures.