Liam Floyd - Academia.edu (original) (raw)

Papers by Liam Floyd

Solid-State Electronics, 1994

ABSTRACT

ICMTS 2001. Proceedings of the 2001 International Conference on Microelectronic Test Structures (Cat. No.01CH37153)

In this paper, a novel method for the estimation of confidence intervals of extracted parameter v... more In this paper, a novel method for the estimation of confidence intervals of extracted parameter values is proposed. The technique is based on a bootstrap method which evaluates the error distributions which are associated with parameter extraction techniques. Using this technique, a confidence interval can then be estimated for extracted parameter values. Results are presented for DC, capacitance and high

Solid-State Electronics, 2021

Abstract We investigate the interplay between the series (S) and parallel (P) equivalent circuit ... more Abstract We investigate the interplay between the series (S) and parallel (P) equivalent circuit representations of the MOS system conductance (G) and capacitance (C) in inversion. Experimental and simulated data for Si and InGaAs MOSCAPs are firstly analyzed mathematically. It is found that by interpreting the measured data in both the series and parallel mode, five independent values are obtained for the magnitude and frequency of the maxima and minima points of the −ωdCS,P/dω and GS,P/ω functions versus angular frequency (ω). The significance and application of the approach is presented and discussed.

2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2019

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ECS Meeting Abstracts, 2017

Proceedings of the 2015 International Conference on Microelectronic Test Structures, 2015

We link up with the recent literature on the differentiated MNC with its stress on intra-MNC know... more We link up with the recent literature on the differentiated MNC with its stress on intra-MNC knowledge flows. However, rather than focusing on the characteristics of knowledge as determinants of knowledge transfer within MNCs, we focus instead on levels of knowledge in subsidiaries, the sources of transferable subsidiary knowledge, and on the organizational means and conditions that realize knowledge transfer as the relevant determinants. We find largely positive support for the relevant hypotheses which are tested on a unique dataset on knowledge development in subsidiary firms (the Centre of Excellence-project).

IEEE Transactions on Electron Devices, 2014

Experimental observations for the In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system in in... more Experimental observations for the In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system in inversion indicate that the measured capacitance (C) and conductance (G or G m), are uniquely related through two functions of the alternating current angular frequency (ω). The peak value of the first function (G/ω) is equal to the peak value of the second function (−dC/dlog e (ω) ≡ −ωdC/dω). Moreover, these peak values occur at the same angular frequency (ω m), that is, the transition frequency. The experimental observations are confirmed by physics-based simulations, and applying the equivalent circuit model for the MOS system in inversion, the functional relationship is also demonstrated mathematically and shown to be generally true for any MOS system in inversion. The functional relationship permits the discrimination between high interface state densities and genuine surface inversion. The two function peak values are found to be equal to C 2 ox /(2(C ox + C D)) where C ox is the oxide capacitance per unit area and C D is the semiconductor depletion capacitance in inversion. The equal peak values of the functions, and their observed symmetry relation about ω m on a logarithmic ω plot, opens a new route to experimentally determining C ox. Finally, knowing ω m permits the extraction of the minority carrier generation lifetime in the bulk of the In 0.53 Ga 0.47 As layer.

Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology, 2004

A comparative evaluation of the leading lead-free solder candidate (95.5Sn3.8Ag0.7Cu) and traditi... more A comparative evaluation of the leading lead-free solder candidate (95.5Sn3.8Ag0.7Cu) and traditional tin-lead solder (63Sn37Pb) under thermal cycling conditions was carried out. A test vehicle consisting of four daisy chained 10×10 array 0.8mm pitch plastic micro ball grid arrays (microBGA) mounted on an 8-layer FR4 printed wiring board was designed. The board finish was organic solder preservative (OSP) for the lead-free devices and hot air solder levelled (HASL) in the case of the eutectic devices. An event detector was used to monitor the continuity of each daisy chain during accelerated temperature cycling, where the test vehicles were cycled with a ramp rate of approximately 3°C per minute from −40°C to 125°C, with 10-minute dwells and a total cycle time of 2 hours 10 minutes. Results to date plotted using a Weibull distribution indicate that the SnAgCu solder is more reliable under these conditions. Experiments were also carried out on large-scale lead-free solder specimens t...

SPIE proceedings …, 2001

Résumé/Abstract The effects of solder flux residues on the electrical functionality of RF circuit... more Résumé/Abstract The effects of solder flux residues on the electrical functionality of RF circuit boards are investigated in this paper. The electrical characteristics of the residues are tested in terms of the change in response of microstrip resonator structures caused by ...

Semiconductor Science and Technology, 2012

ABSTRACT We present a systematic study of Si dopant implantation and activation in p-type In0.53G... more ABSTRACT We present a systematic study of Si dopant implantation and activation in p-type In0.53Ga0.47As in an attempt to optimize the source and drain regions of an n-channel III-V metal–oxide–semiconductor field-effect transistor. Test structures based on the transfer length method were fabricated on Si-implanted p-In0.53Ga0.47As/p-InP buffer/semi-insulting InP. A Doehlert design of experiment (DOE) was used to investigate the effect of annealing temperature and time on the electrical properties of the samples. The DOE covered an experimental domain of 625–725 °C and 15–45 s. The current–voltage characteristics of all tested structures exhibited excellent ohmic behavior. The DOE revealed a minimum sheet resistance of (195.6 ± 3.4) Ω/□ for an optimum anneal condition of 715 °C for 32 s. Nonalloyed Au/Ge/Au/Ni/Au contacts, on the sample annealed at 675 °C for 30 s (center point of the experimental domain), exhibited a low specific contact resistance of (7.4 ± 4.5) × 10−7 Ω cm2. The sample annealed at 675 °C for 30 s was further investigated using secondary ion mass spectrometry (SIMS) and cross-sectional transmission electron microscopy (XTEM) analyses. SIMS revealed that Si ions did not diffuse with annealing, while XTEM showed the formation of characteristic loop defects potentially responsible for the sheet resistance and specific contact resistance degradation.

Nanotechnology, 2011

Conjugated polymer based 1D nanostructures are attractive building blocks for future opto-electro... more Conjugated polymer based 1D nanostructures are attractive building blocks for future opto-electronic nanoscale devices and systems. However, a critical challenge remains the lack of manipulation methods that enable controlled and reliable positioning and orientation of organic nanostructures in a fast, reliable and scalable manner. To address this challenge, we explore dielectrophoretic assembly of discrete poly(9,9-dioctylfluorene) nanofibres and demonstrate site selective assembly and orientation of these fibres. Nanofibre arrays were assembled preferentially at receptor electrode edges, being aligned parallel to the applied electric field with a high order parameter fit (∼ 0.9) and exhibiting an emission dichroic ratio of ∼ 4.0. As such, the dielectrophoretic method represents a fast, reliable and scalable self-assembly approach for manipulation of 1D organic nanostructures. The ability to fabricate nanofibre arrays in this manner could be potentially important for exploration and development of future nanoscale opto-electronic devices and systems.

Microelectronic Engineering, 1997

Numerical techniques used to model lossless quasi-TEM behaviour of multilevel interconnects are d... more Numerical techniques used to model lossless quasi-TEM behaviour of multilevel interconnects are discussed and are then applied to a two layer, five conductor interconnect structure of typical IC dimensions. Comparisons are made between RC delays in AI/SiO 2 and Cu/BCB interconnect showing an approximately 40% delay reduction with the high conductivity, low dielectric constant combination.

International Journal of Heat and Mass Transfer, 2005

The usual equation for the converging wave method [P. Cielo, L.A. Utracki, M. Lamontagne, Thermal... more The usual equation for the converging wave method [P. Cielo, L.A. Utracki, M. Lamontagne, Thermal diffusivity measurements by the converging thermal-wave technique, Canad. J. Phys. 64 (1986) 1172–1177] for thermal diffusivity measurements assumes idealised conditions that are difficult to achieve in a real experimental situation and this hinders the extraction of diffusivity values. A model for thermal transport is described

Journal of Applied Physics, 2009

In pursuit of thin film ferroelectric materials for frequency agile applications that are both ea... more In pursuit of thin film ferroelectric materials for frequency agile applications that are both easily adapted to large area deposition and also high performance, an investigation has been carried out into sol-gel deposition of 3% Mn doped ͑Pb 0.4 Sr 0.6 ͒TiO 3. Large area capability has been demonstrated by growth of films with good crystallinity and grain structure on 4 in. Si wafers. Metal-insulator-metal capacitors have also been fabricated and development of an improved de-embedding technique that takes parasitic impedances fully into account has enabled accurate extraction of the high frequency dielectric properties of the Pb x Sr 1−x TiO 3 films. Practically useful values of ϳ 1000, tan ␦ ϳ 0.03, and tunability ϳ50% have been obtained in the low gigahertz range ͑1-5 GHz͒. Peaks in the dielectric loss due to acoustic resonance have been modeled and tentatively identified as due to an electrostrictive effect with an electromechanical coupling coefficient of ϳ0.04 at an electric field of 240 kV/cm which is potentially useful for tunable thin film bulk acoustic wave devices.

A novel technique has been developed, which is sensitive to the degree of voiding damage induced ... more A novel technique has been developed, which is sensitive to the degree of voiding damage induced in a wide-line interconnect test structure (Testing of conductors, Preliminary Irish patent application, August 26th, 1998). The technique is based on the measurement of the scattering parameters (S-parameters) of a simple, metal-line test structure over a range of high frequencies. The transmission-line parameter, G (leakage conductance), which is calculated from the S-parameter measurements, is shown to be sensitive to distribute voiding, especially in wider lines. This is signi®cant for the following reasons: (1) the measurement is fast Ð a few seconds per test structure, (2) it can be performed at wafer level, (3) it does not rely on overstressing of the metallization and (4) it is sensitive to the amount of voiding damage present in wide interconnect lines. Potential applications for this technique are: (a) an in-line statistical reliability control (SRC) test for the detection of stress voids induced during processing, and (b) an in-line SRC test for electromigration when preceded by a suitable current pre-stress step. #

IEEE Transactions on Semiconductor Manufacturing, 2003

In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work ... more In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favorably with those extracted using S-parameter measurements. Additionally, methods are formulated to reduce the number of data points required for parameter extraction while at the same time maintaining a high model accuracy.

The integration of Schottky diode submillimetre wave circuits on GaAs membranes, and the transfer... more The integration of Schottky diode submillimetre wave circuits on GaAs membranes, and the transfer of the circuit to a lower dielectric membrane substrate is discussed. Two 366GHz mixers were designed to demonstrate the membrane approach using post processing of commercial foundry processed wafers.

We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field eff... more We present the development of a high-k first n-channel InGaAs metal-oxide-semiconductor field effect transistors (MOSFETs) and the effect of annealing on the source/drain (S/D) sheet resistance (Rs) and the high-k gate oxide. Test structures based on the transfer length method (TLM) were used as part of a design of experiment (DOE) to optimize the S/D implant activation process. The optimized process was 715°C for 32 s, leading to a minimum Rs of (195.6 ± 3.4) Ω/d. Metal-oxide-semiconductor capacitors (MOSCAPs) with a 2 nm Al2O3/8 nm HfO2 gate oxide were annealed at 675°C, 700°C and 725°C for 30 s. Leakage current lower than 2.1×10-8 A/cm2 were obtained for electric fields of ~3 MV/cm and low frequency dispersion of capacitance in accumulation (<;1.7%) were obtained. Densities of interface states (DIT) were estimated using the conductance method. The output characteristics of a 5-μm gate length MOSFET annealed at 650°C is presented.

The design, fabrication and testing of broadband fixed-tuned 183 GHz and 366 GHz sub-harmonic mix... more The design, fabrication and testing of broadband fixed-tuned 183 GHz and 366 GHz sub-harmonic mixers is discussed. Two mixer circuits using planar Schottky diodes monolithically integrated with RF/LO and IF matching and filtering networks onto a 3.7 um thick GaAs membrane are presented. The mixers were designed and fabricated using a novel approach in post processing of commercial foundry wafers. The double sideband measurements at room temperature on the 183 GHz sub-harmonic mixer yielded conversion loss and noise temperature of 4.9 dB and 608 K, respectively. The measured double sideband conversion loss and noise temperature of the 366 GHz mixer were 6.9 dB and 1220 K, respectively. To the authors' knowledge these are the best published results for sub-harmonic MMIC membrane mixers at these frequencies.

Journal of Materials Chemistry, 2005

... E-mail: aidan.quinn@tyndall.ie , gareth.redmond@tyndall.ie. b Department of Chemistry, Univer... more ... E-mail: aidan.quinn@tyndall.ie , gareth.redmond@tyndall.ie. b Department of Chemistry, University of Ferrara, Via Luigi Borsari, 46 ... R increases monotonically with decreasing T, consistent with the NeugebauerWebb model for tunnel transport through an array of isolated, size ...