Mahesh Nanjundappa - Academia.edu (original) (raw)
Papers by Mahesh Nanjundappa
Formally-based design and implementation techniques for complex safety-critical embedded systems ... more Formally-based design and implementation techniques for complex safety-critical embedded systems are required not only to handle the complexity, but also to provide correctness guarantees. Traditional design approaches struggle to cope with complexity, and they generally require extensive testing to guarantee correctness. As the designs get larger and more complex, traditional approaches face many limitations. An alternate design approach is to adopt a "correct-by-construction" paradigm and synthesize the desired hardware and software from the high-level descriptions expressed using one of the many formal modeling languages. Since these languages are equipped with formal semantics, formally-based tools can be employed for various analysis. In this dissertation, we adopt one such formal modeling language-MRICDF (Multi-Rate Instantaneous Channel-connected Data Flow). MRICDF is a graphical, declarative, polychronous modeling language, with a formalism that allows the modeler to easily describe multi-clocked systems without the necessity of global clock. Unnecessary synchronizations among concurrent computation entities can be avoided using a polychronous language such as MRICDF. We have explored a Boolean theory-based techniques for synthesizing multi-threaded/concurrent code and extended the technique to improve the performance of synthesized multi-threaded code. We also explored synthesizing ASIPs (Application Specific Instruction Set Processors) from MRICDF models. Further, we have developed formal techniques to identify constructive causality in polychronous models. We have also developed SMT (Satisfiablity Modulo Theory)-based techniques to identify dimensional inconsistencies and to perform value-range analysis of polychronous models.
2012 Electronic System Level Synthesis Conference, 2012
Polychrony, a model of computation, allows us to statically analyze safety properties from formal... more Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how integrating a Satisfiability Modulo Theory (SMT) solver to POLYCHRONY compiler can enhance its decision making capabilities. Further, we show, how a polyhedral analysis library integrated to the compiler, can compute safe operational boundaries, and filter unsafe input combinations to keep the system safe. We enhanced the POLYCHRONY compiler's ability to make more accurate decisions and to accept and characterize the safe input range for specificatio...
Electronic design automation (EDA) tools play a central role in bridging the productivity gap for... more Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today’s design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes ( 3 ) of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of ...
: This report discussed the fundamental theory, algorithms, and prototype tools for the synthesis... more : This report discussed the fundamental theory, algorithms, and prototype tools for the synthesis of embedded safety-critical software for multi-core embedded platforms as well as to initiate planned technology transfer to a Department of Defense (DoD) vender company. The techniques and tools developed during project execution will enable the production of embedded safety -critical software with improved quality and performance, decreases in cost and development times, automation of labor-intensive and error -prone processes, increased reliability, and easier integration and sustainment.
Proceedings of the 2014 Forum on Specification and Design Languages (FDL), 2014
Cyber physical systems are characterized by continuous interaction between digital control system... more Cyber physical systems are characterized by continuous interaction between digital control systems and physical systems. To design critical control software that is to be used in control systems, a modeldriven correct-by-construction approach is preferable. Modeling languages based on synchronous model of time - such as Simulink, State Chart, Esterel, Lustre etc., are often used for sequential software synthesis and languages with a polychronous timing model such as Signal, MRICDF (Multi-Rate Instantaneous Channel-connected Data Flow) etc., are often used for concurrent software synthesis. The interfaces of such software to the real world are through digital signals that are often sampled quantities of physical entities - such as velocity, acceleration, pressure etc. Standard type systems available in programming or modeling languages assign traditional data types such as float, real etc., to these signals. Modelers might mistakenly connect two signals with the same traditional data types but representing different physical entities leading to critical bugs in the synthesized software. Early detection of such mistakes require enhanced type system and type checking algorithms. In this work, we attempt to extend the type system of the polychronous modeling language MRICDF and propose type inference techniques that consider the physical dimensions and units of the signals along with the data types. We also propose an SMT (Satisfiability Modulo Theories) based verification approach that verifies type consistency and provides invariants under which the type consistency is upheld.
Abstract : This is the final report on the findings of the AFRL funded project A Formal Approach ... more Abstract : This is the final report on the findings of the AFRL funded project A Formal Approach to the Provably Correct Synthesis of Mission Critical Embedded Software for Multi-core Platforms. In this work we enhanced the theory of a formal modeling language based specifications, namely MRICDF. We demonstrated an implementation of a software specification and code synthesis tool based on MRICDF. The work entails new synthesis algorithms, characterization of specifications, formal proof techniques for proving the correctness preservation property of the refinement steps in our step-wise refinement oriented synthesis technique, multi-core code synthesis, endowing the specification with platform specific worst case execution times to check real-time schedulability, and some case studies.
Electronic design automation (EDA) tools play a central role in bridging the productivity gap for... more Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes (2 3) rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using Sys-temC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs offer parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers.
Page 1. ACSD 2011 Additional Reviewers Alessandro Aldini Sidharta Andalam Yu Bai David Bañeres De... more Page 1. ACSD 2011 Additional Reviewers Alessandro Aldini Sidharta Andalam Yu Bai David Bañeres Debjyoti Bera Simona Bernardi Milos Blagojevic Vaclav Brozek Georgel Calin Taolue Chen Pieter Cuijpers Gian-Luca Dei Rossi Rafael Dos Santos Doug Down Unmesh Dutta Bordoloi Dirk Fahland Alessandro Fantechi Emmanuel Filiot Vojtech Forejt Joaquim Gabarro Marc Geilen Felipe Ghellar Henri Hansen Marcos Hervé Jing Huang Reiner Hüchting Jorge Júlvez Swarup Kumar Mohalik Kari Kähkönen Sébastien Lafond Alberto Lluch Lafuente ...
Abstract: This final report contains the findings from the trustworthy composition of pre-designe... more Abstract: This final report contains the findings from the trustworthy composition of pre-designed software components project. Since DoD software is often developed at multiple vendor sites, individual components may be verified and delivered to an integrator--but the integration might fail because of behavioral incompatibility of the component interfaces. This work proposed behavioral types of interfaces by extracting the polychronous model from source code, and then using the theory of polychronous composition to check if the ...
Recent developments in graphics processing unit (GPU) technology has invigorated an interest in u... more Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of multiple central processing units, and ...
Proceedings of the 2nd FME Workshop on Formal Methods in Software Engineering - FormaliSE 2014, 2014
Polychrony, a model of computation, allows us to statically analyze safety properties from formal... more Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how ...
SystemC promises an environment for faster hardware/ software design-space exploration.
The main objective of this paper is to speed up the simulation performance of SystemC designs at ... more The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today's general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC's discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC reference implementation, our threading model is capable of executing in parallel on the large number of simple processing units available on GPUs. Our simulation infrastructure is called SCGPSim and it includes a source-to-source (S2S) translator to transform synthesizable SystemC models into parallelly executable programs targeting an NVIDIA GPU. The translator retains the simulation semantics of the original designs by applying semantics preserving transformations. The resulting transformed models mapped onto the massively parallel architecture of GPUs improve simulation efficiency quite substantially. Preliminary experiments with varying-sized examples such as AES, ALU, and FIR have shown simulation speed-ups ranging from 30?? to 100??. Considering that our transformations are not yet optimized, we believe that optimizing them will improve the simulation performance even further.
Formally-based design and implementation techniques for complex safety-critical embedded systems ... more Formally-based design and implementation techniques for complex safety-critical embedded systems are required not only to handle the complexity, but also to provide correctness guarantees. Traditional design approaches struggle to cope with complexity, and they generally require extensive testing to guarantee correctness. As the designs get larger and more complex, traditional approaches face many limitations. An alternate design approach is to adopt a "correct-by-construction" paradigm and synthesize the desired hardware and software from the high-level descriptions expressed using one of the many formal modeling languages. Since these languages are equipped with formal semantics, formally-based tools can be employed for various analysis. In this dissertation, we adopt one such formal modeling language-MRICDF (Multi-Rate Instantaneous Channel-connected Data Flow). MRICDF is a graphical, declarative, polychronous modeling language, with a formalism that allows the modeler to easily describe multi-clocked systems without the necessity of global clock. Unnecessary synchronizations among concurrent computation entities can be avoided using a polychronous language such as MRICDF. We have explored a Boolean theory-based techniques for synthesizing multi-threaded/concurrent code and extended the technique to improve the performance of synthesized multi-threaded code. We also explored synthesizing ASIPs (Application Specific Instruction Set Processors) from MRICDF models. Further, we have developed formal techniques to identify constructive causality in polychronous models. We have also developed SMT (Satisfiablity Modulo Theory)-based techniques to identify dimensional inconsistencies and to perform value-range analysis of polychronous models.
2012 Electronic System Level Synthesis Conference, 2012
Polychrony, a model of computation, allows us to statically analyze safety properties from formal... more Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how integrating a Satisfiability Modulo Theory (SMT) solver to POLYCHRONY compiler can enhance its decision making capabilities. Further, we show, how a polyhedral analysis library integrated to the compiler, can compute safe operational boundaries, and filter unsafe input combinations to keep the system safe. We enhanced the POLYCHRONY compiler's ability to make more accurate decisions and to accept and characterize the safe input range for specificatio...
Electronic design automation (EDA) tools play a central role in bridging the productivity gap for... more Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today’s design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes ( 3 ) of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of ...
: This report discussed the fundamental theory, algorithms, and prototype tools for the synthesis... more : This report discussed the fundamental theory, algorithms, and prototype tools for the synthesis of embedded safety-critical software for multi-core embedded platforms as well as to initiate planned technology transfer to a Department of Defense (DoD) vender company. The techniques and tools developed during project execution will enable the production of embedded safety -critical software with improved quality and performance, decreases in cost and development times, automation of labor-intensive and error -prone processes, increased reliability, and easier integration and sustainment.
Proceedings of the 2014 Forum on Specification and Design Languages (FDL), 2014
Cyber physical systems are characterized by continuous interaction between digital control system... more Cyber physical systems are characterized by continuous interaction between digital control systems and physical systems. To design critical control software that is to be used in control systems, a modeldriven correct-by-construction approach is preferable. Modeling languages based on synchronous model of time - such as Simulink, State Chart, Esterel, Lustre etc., are often used for sequential software synthesis and languages with a polychronous timing model such as Signal, MRICDF (Multi-Rate Instantaneous Channel-connected Data Flow) etc., are often used for concurrent software synthesis. The interfaces of such software to the real world are through digital signals that are often sampled quantities of physical entities - such as velocity, acceleration, pressure etc. Standard type systems available in programming or modeling languages assign traditional data types such as float, real etc., to these signals. Modelers might mistakenly connect two signals with the same traditional data types but representing different physical entities leading to critical bugs in the synthesized software. Early detection of such mistakes require enhanced type system and type checking algorithms. In this work, we attempt to extend the type system of the polychronous modeling language MRICDF and propose type inference techniques that consider the physical dimensions and units of the signals along with the data types. We also propose an SMT (Satisfiability Modulo Theories) based verification approach that verifies type consistency and provides invariants under which the type consistency is upheld.
Abstract : This is the final report on the findings of the AFRL funded project A Formal Approach ... more Abstract : This is the final report on the findings of the AFRL funded project A Formal Approach to the Provably Correct Synthesis of Mission Critical Embedded Software for Multi-core Platforms. In this work we enhanced the theory of a formal modeling language based specifications, namely MRICDF. We demonstrated an implementation of a software specification and code synthesis tool based on MRICDF. The work entails new synthesis algorithms, characterization of specifications, formal proof techniques for proving the correctness preservation property of the refinement steps in our step-wise refinement oriented synthesis technique, multi-core code synthesis, endowing the specification with platform specific worst case execution times to check real-time schedulability, and some case studies.
Electronic design automation (EDA) tools play a central role in bridging the productivity gap for... more Electronic design automation (EDA) tools play a central role in bridging the productivity gap for designing complex hardware systems. However, with an increase in the size and complexity of today's design requirements, current methodologies and EDA tools are unable to effectively mitigate the further widening of productivity gap. It is estimated that testing and verification takes (2 3) rd of the total development time of complex hardware systems. Functional simulation forms the main stay of testing and verification process and is the most widely used technique for testing and verification. Most of the simulation algorithms and their implementations are designed for uniprocessor systems that cannot easily leverage the parallelism in multi-core and GPU platforms. For example, logic simulation often uses levelized sequential algorithms, whereas the discrete-event simulation frameworks for Verilog, VHDL and SystemC employ concurrency in the form of multi-threading to given an illusion of the inherent parallelism present in circuits. However, the discrete-event model of computation requires a global notion of an event-queue, which makes improving its simulation performance via parallelization even more challenging. This work investigates automatic parallelization of simulation algorithms used to simulate hardware models. In particular, we focus on parallelizing the simulation of hardware designs described at the RTL using Sys-temC/HDL with examples to clearly describe the parallelization. Even though multi-cores and GPUs offer parallelism, efficiently exploiting this parallelism with their programming models is not straightforward. To overcome this, we also focus our research on building intelligent translators to map simulation applications onto multi-cores and GPUs such that the complexity of the low-level programming models is hidden from the designers.
Page 1. ACSD 2011 Additional Reviewers Alessandro Aldini Sidharta Andalam Yu Bai David Bañeres De... more Page 1. ACSD 2011 Additional Reviewers Alessandro Aldini Sidharta Andalam Yu Bai David Bañeres Debjyoti Bera Simona Bernardi Milos Blagojevic Vaclav Brozek Georgel Calin Taolue Chen Pieter Cuijpers Gian-Luca Dei Rossi Rafael Dos Santos Doug Down Unmesh Dutta Bordoloi Dirk Fahland Alessandro Fantechi Emmanuel Filiot Vojtech Forejt Joaquim Gabarro Marc Geilen Felipe Ghellar Henri Hansen Marcos Hervé Jing Huang Reiner Hüchting Jorge Júlvez Swarup Kumar Mohalik Kari Kähkönen Sébastien Lafond Alberto Lluch Lafuente ...
Abstract: This final report contains the findings from the trustworthy composition of pre-designe... more Abstract: This final report contains the findings from the trustworthy composition of pre-designed software components project. Since DoD software is often developed at multiple vendor sites, individual components may be verified and delivered to an integrator--but the integration might fail because of behavioral incompatibility of the component interfaces. This work proposed behavioral types of interfaces by extracting the polychronous model from source code, and then using the theory of polychronous composition to check if the ...
Recent developments in graphics processing unit (GPU) technology has invigorated an interest in u... more Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of multiple central processing units, and ...
Proceedings of the 2nd FME Workshop on Formal Methods in Software Engineering - FormaliSE 2014, 2014
Polychrony, a model of computation, allows us to statically analyze safety properties from formal... more Polychrony, a model of computation, allows us to statically analyze safety properties from formal specifications and synthesize deterministic software for safety-critical cyber physical systems. Currently, the analysis is performed on the formal specifications through Boolean abstractions. Even though it is a sound abstraction, for more precise analysis we might have to refine the abstraction. Refining the abstraction level from pure Boolean to a theory of Integers can lead to more precise decisions. In this paper, we first show how ...
SystemC promises an environment for faster hardware/ software design-space exploration.
The main objective of this paper is to speed up the simulation performance of SystemC designs at ... more The main objective of this paper is to speed up the simulation performance of SystemC designs at the RTL abstraction level by exploiting the high degree of parallelism afforded by today's general purpose graphics processors (GPGPUs). Our approach parallelizes SystemC's discrete-event simulation (DES) on GPGPUs by transforming the model of computation of DES into a model of concurrent threads that synchronize as and when necessary. Unlike the cooperative threading model employed in the SystemC reference implementation, our threading model is capable of executing in parallel on the large number of simple processing units available on GPUs. Our simulation infrastructure is called SCGPSim and it includes a source-to-source (S2S) translator to transform synthesizable SystemC models into parallelly executable programs targeting an NVIDIA GPU. The translator retains the simulation semantics of the original designs by applying semantics preserving transformations. The resulting transformed models mapped onto the massively parallel architecture of GPUs improve simulation efficiency quite substantially. Preliminary experiments with varying-sized examples such as AES, ALU, and FIR have shown simulation speed-ups ranging from 30?? to 100??. Considering that our transformations are not yet optimized, we believe that optimizing them will improve the simulation performance even further.