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International Journal of Engineering Research and Applications (IJERA)
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In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, whi... more In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30 % to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper various power efficient flip- flops with low power clock distribution network are examined. Among these flips-flops low Power Clocked Pass Transistor Flip-Flop (LCPTFF) consumes least power than Clocked Pair Shared Flip-Flop (CPSFF), Conditional Data Mapping Flip-Flop and Conditional Discharge Flip-Flop
International Journal of Computer Applications, 2013
2013 Sixth International Conference on Contemporary Computing (IC3), 2013
ABSTRACT Power consumption plays an imperative role specifically in the field of VLSI today, ever... more ABSTRACT Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The core of this paper consist of the introduction of a novel and high performance design of an 8×8 multiplier using ancient Indian mathematics called Vedas. We have presented three different designs of the 8×8 Vedic multiplier using the CMOS technology, PTL and finally concoct the Vedic Multiplier using the Multi-Threshold Voltage CMOS (MTCMOS) and proved that the MTCMOS implementation of Vedic Multiplier is the best among all the implementations. The multiplier and the adder-subtractor units used for the implementation of Vedic multiplier are adopted from ancient methodology of India mathematics called as Vedas. The use of Vedas not only abates the carry propagation taking place from lsb to msb but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power than any other type of multipliers in the literature. The functionality of all the three designs and there PDP and total power consumptions at two different frequencies and three different voltages were calculated on tanner EDA 13.0v. The proposed MTCMOS implementation of Vedic multiplier is up to 24.55% power efficient and about 97.54% speedy as compared to the conventional CMOS implementation of Vedic multiplier.
2013 3rd IEEE International Advance Computing Conference (IACC), 2013
International Journal of Computer Applications, 2013
Page 1. THE COMPLETE CLASSIC TEXT DELUXE EDITION Napoleon Hill Page 2. Page 3. Page 4. Page 5. TH... more Page 1. THE COMPLETE CLASSIC TEXT DELUXE EDITION Napoleon Hill Page 2. Page 3. Page 4. Page 5. THINK and GROW RICH DELUXE EDITION Thl. One 2BE0-0WH-WL.9C Page 6. Jeremy P. Tarcher/Penguin a member of Penguin Group (USA) Inc. New York Page 7. ...
In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, whi... more In Integrated circuits a gargantuan portion of on chip power is expended by clocking systems, which comprises of timing elements such as flip-flops, latches and clock distribution network. These elements absorb approximately 30 % to 60% of the total power dissipation in the system. In order to design high performance and power efficient circuits a scrupulous approach should be adopted to reduce the power consumed by flip-flops and latches. In this paper various power efficient flip- flops with low power clock distribution network are examined. Among these flips-flops low Power Clocked Pass Transistor Flip-Flop (LCPTFF) consumes least power than Clocked Pair Shared Flip-Flop (CPSFF), Conditional Data Mapping Flip-Flop and Conditional Discharge Flip-Flop
International Journal of Computer Applications, 2013
2013 Sixth International Conference on Contemporary Computing (IC3), 2013
ABSTRACT Power consumption plays an imperative role specifically in the field of VLSI today, ever... more ABSTRACT Power consumption plays an imperative role specifically in the field of VLSI today, every designer be it an analog circuit or a digital circuit designer is concerned about the amount of power his or her circuit is going to consume in the end. The core of this paper consist of the introduction of a novel and high performance design of an 8×8 multiplier using ancient Indian mathematics called Vedas. We have presented three different designs of the 8×8 Vedic multiplier using the CMOS technology, PTL and finally concoct the Vedic Multiplier using the Multi-Threshold Voltage CMOS (MTCMOS) and proved that the MTCMOS implementation of Vedic Multiplier is the best among all the implementations. The multiplier and the adder-subtractor units used for the implementation of Vedic multiplier are adopted from ancient methodology of India mathematics called as Vedas. The use of Vedas not only abates the carry propagation taking place from lsb to msb but also produces the partial product and there sums in the same step. Vedic mathematics based multipliers thus causes least delay and consume least power than any other type of multipliers in the literature. The functionality of all the three designs and there PDP and total power consumptions at two different frequencies and three different voltages were calculated on tanner EDA 13.0v. The proposed MTCMOS implementation of Vedic multiplier is up to 24.55% power efficient and about 97.54% speedy as compared to the conventional CMOS implementation of Vedic multiplier.
2013 3rd IEEE International Advance Computing Conference (IACC), 2013
International Journal of Computer Applications, 2013
Page 1. THE COMPLETE CLASSIC TEXT DELUXE EDITION Napoleon Hill Page 2. Page 3. Page 4. Page 5. TH... more Page 1. THE COMPLETE CLASSIC TEXT DELUXE EDITION Napoleon Hill Page 2. Page 3. Page 4. Page 5. THINK and GROW RICH DELUXE EDITION Thl. One 2BE0-0WH-WL.9C Page 6. Jeremy P. Tarcher/Penguin a member of Penguin Group (USA) Inc. New York Page 7. ...