Manoj Raj Saxena - Academia.edu (original) (raw)
Papers by Manoj Raj Saxena
International Journal of VLSI Design & Communication Systems, 2011
The paper presents a simulation study of effect of interface fixed charges on the performance of ... more The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect of hot carrier damage/stress induced damage/process damage/radiation damage induced fixed charges at the semiconductor-oxide interface of the cylindrical nanowire MOSFET. Also the circuit reliability issues of the device are discussed in terms of the performance degradation due to interface fixed charges. The performance has been compared for the three materials in terms of drain current driving capability, I on /I off ratio, early voltage, transconductance, parasitic gate capacitance, intrinsic delay, current gain and power gain of the device.
International Journal of VLSI Design & Communication Systems, 2011
... RAKHI NARANG 1 , MANOJ SAXENA 2 , RS GUPTA 3 AND MRIDULA GUPTA 1 ... Electronic Science, Univ... more ... RAKHI NARANG 1 , MANOJ SAXENA 2 , RS GUPTA 3 AND MRIDULA GUPTA 1 ... Electronic Science, University of Delhi, South Campus, New Delhi, India rakhinarang@gmail.com, mridula@south.du.ac.in 2Department of Electronics, Deen Dayal Upadhyaya College, University ...
2012 International Conference on Emerging Electronics, 2012
ABSTRACT This work presents an analytical model for a dielectric modulated (DM) double gate (DG) ... more ABSTRACT This work presents an analytical model for a dielectric modulated (DM) double gate (DG) MOSFET working as a biosensor. The sensitivity is quantified in terms of relative change in the threshold voltage and sub-threshold drain current derived using the model. The impact of various device geometrical parameters (i.e. channel thickness, nanogap cavity length and thickness) on the sensitivity has been also been investigated. Moreover, two types of architecture: Nanogap embedded DG-FET with a nanogap cavity at the source/drain etched in the oxide and other with complete cavity over the channel length are analyzed through the model.
2012 International Conference on Emerging Electronics, 2012
ABSTRACT
High Performance Devices - Proceedings of the 2004 IEEE Lester Eastman Conference, 2005
2007 International Workshop on Physics of Semiconductor Devices, 2007
We have presented a two dimensional closed form analytical subthreshold model for graded channel ... more We have presented a two dimensional closed form analytical subthreshold model for graded channel (GC) double gate fully depleted SOI n-MOSFET with gate misalignment effect, using conformal mapping transformation approach. A closed-form compact model, considering the gate misalignment effect in the non-gate overlap region has also been developed.
Microelectronics Reliability, 2012
ABSTRACT
Microelectronics Reliability, 2012
The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with... more The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with localised interface charges. The objective of the present work is to study the performance degradation due to hot carrier induced/radiation induced/stress induced damage in the form of localised/fixed charges at the semiconductor/oxide interface of the device. Impact of fixed charges has been studied on the characteristics such as drain current, transconductance and its higher order terms, device efficiency and linearity FOMs. Effect of nature and extension of interface fixed charges has been discussed in detail through extensive simulation. Circuit reliability issues of the device are discussed in terms of DC bias point degradation.
Environmental Science and Engineering, 2013
The paper presents the comparative study of MESFET as photodetector for three different channel m... more The paper presents the comparative study of MESFET as photodetector for three different channel materials: Si, Ge and GaAs using ATLAS 3D device simulator. Common semi-insulating substrate i.e. sapphire is used for all the three MESFETs. Effect of illumination on the performance of the device has been studied in detail in terms of ratio of dark current to current under illumination, threshold voltage shift and enhanced drain current.
2008 International Conference on Recent Advances in Microwave Theory and Applications, 2008
... Chaujar, Manoj Saxena* and RS Gupta Semiconductor Devices Research Laboratory, Department ofE... more ... Chaujar, Manoj Saxena* and RS Gupta Semiconductor Devices Research Laboratory, Department ofElectronic Science, University ofDelhi South Campus, Benito Juarez road, Dhaula Kuan, New Delhi-ll0021, India, *Department of Electronics, Deen Dayal Upadhyaya College ...
2007 International Workshop on Physics of Semiconductor Devices, 2007
Abstract In this paper, for improving the analog performance of scaled MOS devices, structural d... more Abstract In this paper, for improving the analog performance of scaled MOS devices, structural design involving the integration of Dielectric Pocket (DP) and Dual Material Gate (DMG) onto the conventional MOSFET has been studied by means of Dual Material Gate Insulated ...
2007 International Workshop on Physics of Semiconductor Devices, 2007
Fig.1. Schematic sketch of ISEGaS MOSFET. Channel Length (L) = 100 nm, Dielectric Pocket Thicknes... more Fig.1. Schematic sketch of ISEGaS MOSFET. Channel Length (L) = 100 nm, Dielectric Pocket Thickness (T S ) = 20 nm, Shallow Extension Depth (T H ) = 10nm, Junction Depth (X j ) = 30 nm, T ox1 = 2nm , T ox2 = 1nm,N A = 1x10 17 cm -3 .
2007 International Semiconductor Device Research Symposium, 2007
In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated... more In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET (Fig.l) is performed and the influence of technology variations, such as gate length, negative junction depth (NJD) and gate bias has been investigated using ATLAS device simulator.
2007 Asia-Pacific Microwave Conference, 2007
Abstract RF circuit application requires transistors with low intermodulation distortion and thus... more Abstract RF circuit application requires transistors with low intermodulation distortion and thus, linearity analysis is desired to optimize device structure and circuit design. In this work, RF linearity of Dual Material Gate Insulated Shallow Extension Gate Stack (DMG ISEGaS) ...
2013 Annual IEEE India Conference (INDICON), 2013
ABSTRACT In this work, we propose a Dielectric-Modulated (DM) Double-Gate (DG) Junctionless (JL) ... more ABSTRACT In this work, we propose a Dielectric-Modulated (DM) Double-Gate (DG) Junctionless (JL) Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) which is working as biosensor for the label free electrical detection of the biomolecules. We have studied the characteristics such as surface potential, electric field, energy bands, and drain current of the DM-DG-Junctionless MOSFET by the device simulation. The shift in the threshold voltage has been used as the sensing metric to detect the sensitivity after the biomolecule interacts with the device.
Encyclopedia of RF and Microwave Engineering, 2005
Environmental Science and Engineering, 2013
2013 Annual IEEE India Conference (INDICON), 2013
ABSTRACT This paper presents simulation study of Static characteristics for DMG (Dual Material Ga... more ABSTRACT This paper presents simulation study of Static characteristics for DMG (Dual Material Gate) Hetero-Dielectric (H-D) Tunnel FET. Here, two previously reported device architectures i.e. a DMG Single Dielectric TFET and SMG (Single Material Gate) Hetero-Dielectric TFET have been optimized by tuning the work functions and length and later on their combined impact on the proposed device architecture i.e. DMG Hetero-Dielectric Tunnel FET (DMG H-D TFET) is been studied. Electrical parameters such as threshold voltage, drain current Ids, Sub threshold Slope, Ion to Ioff ratio, ambipolar current Iamb have been studied. Some of the important analog parameters like transconductance gm, drain conductance gd, Output resistance Rout, transconductance generation efficiency gm/Ids have also been studied using ATLAS Device Simulation Software.
16th International Workshop on Physics of Semiconductor Devices, 2012
International Journal of VLSI Design & Communication Systems, 2011
The paper presents a simulation study of effect of interface fixed charges on the performance of ... more The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect of hot carrier damage/stress induced damage/process damage/radiation damage induced fixed charges at the semiconductor-oxide interface of the cylindrical nanowire MOSFET. Also the circuit reliability issues of the device are discussed in terms of the performance degradation due to interface fixed charges. The performance has been compared for the three materials in terms of drain current driving capability, I on /I off ratio, early voltage, transconductance, parasitic gate capacitance, intrinsic delay, current gain and power gain of the device.
International Journal of VLSI Design & Communication Systems, 2011
... RAKHI NARANG 1 , MANOJ SAXENA 2 , RS GUPTA 3 AND MRIDULA GUPTA 1 ... Electronic Science, Univ... more ... RAKHI NARANG 1 , MANOJ SAXENA 2 , RS GUPTA 3 AND MRIDULA GUPTA 1 ... Electronic Science, University of Delhi, South Campus, New Delhi, India rakhinarang@gmail.com, mridula@south.du.ac.in 2Department of Electronics, Deen Dayal Upadhyaya College, University ...
2012 International Conference on Emerging Electronics, 2012
ABSTRACT This work presents an analytical model for a dielectric modulated (DM) double gate (DG) ... more ABSTRACT This work presents an analytical model for a dielectric modulated (DM) double gate (DG) MOSFET working as a biosensor. The sensitivity is quantified in terms of relative change in the threshold voltage and sub-threshold drain current derived using the model. The impact of various device geometrical parameters (i.e. channel thickness, nanogap cavity length and thickness) on the sensitivity has been also been investigated. Moreover, two types of architecture: Nanogap embedded DG-FET with a nanogap cavity at the source/drain etched in the oxide and other with complete cavity over the channel length are analyzed through the model.
2012 International Conference on Emerging Electronics, 2012
ABSTRACT
High Performance Devices - Proceedings of the 2004 IEEE Lester Eastman Conference, 2005
2007 International Workshop on Physics of Semiconductor Devices, 2007
We have presented a two dimensional closed form analytical subthreshold model for graded channel ... more We have presented a two dimensional closed form analytical subthreshold model for graded channel (GC) double gate fully depleted SOI n-MOSFET with gate misalignment effect, using conformal mapping transformation approach. A closed-form compact model, considering the gate misalignment effect in the non-gate overlap region has also been developed.
Microelectronics Reliability, 2012
ABSTRACT
Microelectronics Reliability, 2012
The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with... more The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with localised interface charges. The objective of the present work is to study the performance degradation due to hot carrier induced/radiation induced/stress induced damage in the form of localised/fixed charges at the semiconductor/oxide interface of the device. Impact of fixed charges has been studied on the characteristics such as drain current, transconductance and its higher order terms, device efficiency and linearity FOMs. Effect of nature and extension of interface fixed charges has been discussed in detail through extensive simulation. Circuit reliability issues of the device are discussed in terms of DC bias point degradation.
Environmental Science and Engineering, 2013
The paper presents the comparative study of MESFET as photodetector for three different channel m... more The paper presents the comparative study of MESFET as photodetector for three different channel materials: Si, Ge and GaAs using ATLAS 3D device simulator. Common semi-insulating substrate i.e. sapphire is used for all the three MESFETs. Effect of illumination on the performance of the device has been studied in detail in terms of ratio of dark current to current under illumination, threshold voltage shift and enhanced drain current.
2008 International Conference on Recent Advances in Microwave Theory and Applications, 2008
... Chaujar, Manoj Saxena* and RS Gupta Semiconductor Devices Research Laboratory, Department ofE... more ... Chaujar, Manoj Saxena* and RS Gupta Semiconductor Devices Research Laboratory, Department ofElectronic Science, University ofDelhi South Campus, Benito Juarez road, Dhaula Kuan, New Delhi-ll0021, India, *Department of Electronics, Deen Dayal Upadhyaya College ...
2007 International Workshop on Physics of Semiconductor Devices, 2007
Abstract In this paper, for improving the analog performance of scaled MOS devices, structural d... more Abstract In this paper, for improving the analog performance of scaled MOS devices, structural design involving the integration of Dielectric Pocket (DP) and Dual Material Gate (DMG) onto the conventional MOSFET has been studied by means of Dual Material Gate Insulated ...
2007 International Workshop on Physics of Semiconductor Devices, 2007
Fig.1. Schematic sketch of ISEGaS MOSFET. Channel Length (L) = 100 nm, Dielectric Pocket Thicknes... more Fig.1. Schematic sketch of ISEGaS MOSFET. Channel Length (L) = 100 nm, Dielectric Pocket Thickness (T S ) = 20 nm, Shallow Extension Depth (T H ) = 10nm, Junction Depth (X j ) = 30 nm, T ox1 = 2nm , T ox2 = 1nm,N A = 1x10 17 cm -3 .
2007 International Semiconductor Device Research Symposium, 2007
In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated... more In this paper, an extensive study on the on-state and switching behavior of laterally amalgamated dual material gate concave (L-DUMGAC) MOSFET (Fig.l) is performed and the influence of technology variations, such as gate length, negative junction depth (NJD) and gate bias has been investigated using ATLAS device simulator.
2007 Asia-Pacific Microwave Conference, 2007
Abstract RF circuit application requires transistors with low intermodulation distortion and thus... more Abstract RF circuit application requires transistors with low intermodulation distortion and thus, linearity analysis is desired to optimize device structure and circuit design. In this work, RF linearity of Dual Material Gate Insulated Shallow Extension Gate Stack (DMG ISEGaS) ...
2013 Annual IEEE India Conference (INDICON), 2013
ABSTRACT In this work, we propose a Dielectric-Modulated (DM) Double-Gate (DG) Junctionless (JL) ... more ABSTRACT In this work, we propose a Dielectric-Modulated (DM) Double-Gate (DG) Junctionless (JL) Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) which is working as biosensor for the label free electrical detection of the biomolecules. We have studied the characteristics such as surface potential, electric field, energy bands, and drain current of the DM-DG-Junctionless MOSFET by the device simulation. The shift in the threshold voltage has been used as the sensing metric to detect the sensitivity after the biomolecule interacts with the device.
Encyclopedia of RF and Microwave Engineering, 2005
Environmental Science and Engineering, 2013
2013 Annual IEEE India Conference (INDICON), 2013
ABSTRACT This paper presents simulation study of Static characteristics for DMG (Dual Material Ga... more ABSTRACT This paper presents simulation study of Static characteristics for DMG (Dual Material Gate) Hetero-Dielectric (H-D) Tunnel FET. Here, two previously reported device architectures i.e. a DMG Single Dielectric TFET and SMG (Single Material Gate) Hetero-Dielectric TFET have been optimized by tuning the work functions and length and later on their combined impact on the proposed device architecture i.e. DMG Hetero-Dielectric Tunnel FET (DMG H-D TFET) is been studied. Electrical parameters such as threshold voltage, drain current Ids, Sub threshold Slope, Ion to Ioff ratio, ambipolar current Iamb have been studied. Some of the important analog parameters like transconductance gm, drain conductance gd, Output resistance Rout, transconductance generation efficiency gm/Ids have also been studied using ATLAS Device Simulation Software.
16th International Workshop on Physics of Semiconductor Devices, 2012