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Papers by Masahiro Aoyagi

2. テーパー型超伝導 TSV 作製方法の改善我々が提案するテーパー型超伝導TSVは、ボッシュプロセスによるエッチングでテーパー形状を有する貫通孔を作製し、そこに超伝導材料を堆積して電極... more 2. テーパー型超伝導 TSV 作製方法の改善我々が提案するテーパー型超伝導TSVは、ボッシュプロセスによるエッチングでテーパー形状を有する貫通孔を作製し、そこに超伝導材料を堆積して電極を形成する。しかし、ボッシュプロセスのみでエッチングを行った貫通孔には多くのシリコングラスが確認され(図 1)、シリコングラスの存在は電極材料の厚膜化に繋がる。そこで、エッチング方法の改善を行うことでシリコングラスの除去に成功した(図 2)。次に、Si 基板上に改善した作製方法を用いてトレンチ構造を形成し、超伝導電極 (Nb)を堆積した、導通確認用サンプルを作製し、液体ヘリウム温度でその通電評価を行った。その結果、約 40 mA 以上の臨界電流値が得られた。また、提案する作製方法によるテーパー型超伝導 TSV を用いて、図 3 のような STJ を作製し、特性の評価を行った。詳細については当日報告する。

IEEE Transactions on Magnetics, 1989

This paper describes a design and operations of a Josephson address control unit IC(CTRU) which w... more This paper describes a design and operations of a Josephson address control unit IC(CTRU) which will be used for controlling the instruction sequence of an experimental 4-bit Josephson microcomputer prototype system. The CTRU is composed of three sets of 7 to 10bit wide registers and combinational logic circuits driven by a two-phase mono-polar power supply. 593 4-Junction-Logic(4JL) gates have been used in the circuit and fabricated by using 2.5um NbNloxideINbN junction technology with MO resistors and Si02 insulations. Experimental operations of the circuit have been successfully tested for all the instructions which control the program sequence of the computer system.

2011 IEEE Cool Chips XIV, 2011

ABSTRACT 3D multi-chip stacking is a promising technology poised to help combat the “memory wall”... more ABSTRACT 3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher scalability in its functionality and performance just by increasing the number/type of chips, allows to be manufactured with much more flexibility, and has a better cost/performance than conventional 2D SoC based designs.

Journal of The Japan Institute of Electronics Packaging

IETE Journal of Research

This paper presents the design, fabrication, and characterization of a two-axis tilt angle sensor... more This paper presents the design, fabrication, and characterization of a two-axis tilt angle sensor based on the dielectric liquid capacitive sensing structure. The sensor consists of five electrodes. One electrode serves as the exciting electrode and two pairs of electrodes as sensing electrodes, which are arranged at identical positions surrounding a glass cylinder tube, which is partly filled with dielectric liquid. Based on this unique arrangement, the proposed sensor can detect two components of tilt angle in x-axis and y-axis, simultaneously. A computational simulation and experimental measurements are performed to study the performance of the sensor. The numerical simulation is carried out with a finite element analysis using COMSOL. A prototype of the sensor was fabricated, and its performance was evaluated. The tilt angle sensor was employed on a printed circuit board with a conditioning circuit, which consisted of a 170 kHz sine wave generator, pre-amplifiers, rectifiers, and low pass filters. The experiment results confirmed that the tilt angle sensitivities to x-axis and y-axis are 18.2 mV/° and 58.2 mV/° respectively, with cross-axis sensitivity being less than 5.5% in the linear range. The measured tilt angle resolutions are 0.55° and 0.17° on the x-axis and y-axis respectively.

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

IEEE Transactions on Components, Packaging and Manufacturing Technology

To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage ... more To realize low-cost and damage-less through silicon via (TSV) formation, we evaluated the damage caused by a new wet-chemical Si-wafer thinning/backside via exposure process. Damage at the etched Si subsurface was examined using ballon-ring tests, cross-sectional transmission electron microscopy, and electron energy loss spectroscopy. The die fracture load obtained after this process was higher than those for processes that include a backgrinding step. There was little damage to the etched Si subsurface layer after our new process. We then evaluated the damage in 0.8-µm metal-oxide-semiconductor fieldeffect transistor generated by the new process. The changes in threshold voltage, subthreshold swing, transconductance, and leakage current were very small, even when the wafer was thinned down to 20 µm. Finally, we applied our new process to a Cu/Ta via wafer to evaluate the damage in a TSV. No damaged layers were observed in the TSV, and the leakage current between the TSVs after this process was sufficiently small for practical application.

Microelectronics Reliability

Japanese Journal of Applied Physics

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016

Synthesiology English edition, 2016

IC technologies, and the attempt to increase the integration density seemed to face the limit. Th... more IC technologies, and the attempt to increase the integration density seemed to face the limit. The three-dimensional IC chip stacking technology whereby the IC devices are stacked vertically and packaged is one of the solutions, and expectation for it is rising recently as a technology for semiconductor device stacking that enables the increase of integration density for semiconductor ICs. Therefore, we established the fundamental technology for high-density high-integration electronic hardware construction required for 3D IC chip stacking, and we are working on the R&D of the application phase to create the flow of application system development, while engaging in technical support of massproduction technology that, in practice, should be undertaken by leading companies. 2 Advancement of electronic hardware system integration technology by 3D IC chip stacking and the goal of this research First, we shall review the recent development trends of the electronic hardware system integration technology that advanced the manufacturing technology in response to the demand for high density and high integration to enhance the system performance. The system integration method called the system in package (SIP) Term 1 is gaining attention, where several IC chips are stacked in a semiconductor IC package to integrate them into a certain size electronic system. This method enables stacking in the vertical direction that is different from the planar integration technology of

Microelectronics Reliability, 2016

2015 21st International Workshop on Thermal Investigations of ICs and Systems (THERMINIC), 2015

International Symposium on Microelectronics, 2014

For backside exposure of through-silicon vias (TSVs), we developed a new process using Si/Cu grin... more For backside exposure of through-silicon vias (TSVs), we developed a new process using Si/Cu grinding, chemical mechanical polishing (CMP), cap layer deposition, and alkaline etching of Si. In this process, Si/Cu grinding without Cu burning or smearing was performed by using a novel grinding wheel (vitrified-bond type), with in situ cleaning of the grinding wheel by a high-pressure micro jet. CMP was then performed to remove grinding scratches generated by Si/Cu grinding. Next, slight Cu contamination in the Si region between TSVs was decreased by cap layer deposition and alkaline etching of Si. The cap layer was Ni-B film formed by electroless plating. We also applied the developed process to backside exposure of 4-μm-diameter TSVs. As a result, TSVs were exposed uniformly without grinding scratches and Cu contamination in Si region between TSVs was suppressed to < 2.7×1010 atoms/cm2.

Electrotechnical Laboratory Researches No 939 87 P, May 1, 1992