Matthias Bucher - Academia.edu (original) (raw)

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Papers by Matthias Bucher

Materials Science Forum, 2015

Journal of Telecommunications and Information Technology, Mar 17, 2000

The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over ... more The technology of CMOS large-scale integrated circuits (LSI's) achieved remarkable advances over last 25 year and the progress is expected to continue well into the next century. The progress has been driven by the downsizing of the active devices such as MOSFETs. Approaching these dimensions, MOSFET characteristics cannot be accurately predicted using classical modeling methods currently used in the most common MOSFET models such as BSIM, MM9 etc, without introducing large number of empirical parameters. Various physical effects that needed to be considered while modeling UDSM devices: quantization of the inversion layer, mobility degradation, carrier velocity saturation and overshoot, polydepletion effects, bias dependent source/drain resistances and capacitances, vertical and lateral doping profiles, etc. In this paper, we will discuss the progress in the CMOS technology and the anticipated difficulties of the sub-0.25 µm LSI downsizing. Subsequently, basic MOSFET modeling methodologies that are more appropriate for UDSM MOSFETs will be presented as well. The advances in compact MOSFET devices will be illustrated using application examples of the EPFL EKV model.

Ieee Pes Innovative Smart Grid Technologies Europe, Oct 1, 2014

Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems Mixdes 2010, Jun 24, 2010

Reduced overdrive voltage in advanced CMOS technology requires analog circuitry to operate in mod... more Reduced overdrive voltage in advanced CMOS technology requires analog circuitry to operate in moderate and weak inversion. A systematic analysis of scaling of transconductance, output conductance and intrinsic gain with technology, channel length but also bias conditions is presented for a deep submicron CMOS process. The analog properties are represented versus normalized current, so as to provide an easy means of interpretation and comparison. Measured transconductances and derived quantities such as intrinsic gain are investigated for NMOS and PMOS devices of an 110 nm CMOS technology, covering a large range of channel length and inversion conditions. This reveals novel properties of advanced CMOS technology and some useful guidelines for designers are given.

Iscas, 1995

Recent availability of the EKV (Enz-Krummenacher-Vittoz) MOST model [1] from EPFL in a number of ... more Recent availability of the EKV (Enz-Krummenacher-Vittoz) MOST model [1] from EPFL in a number of circuit simulators facilitates the intuitive design, analysis and simulation of analogue and mixed-mode circuits and systems exploring the numerous modes of operation of the MOST [2], particularly at low-voltage (LV) and low-current (LC). A practical approach for either extracting the most critical parameters and/or adapting those already available from widely used SPICE models (levels 2 and 3) for use with the EKV model is presented and opportunities for engineering education are considered. The effectiveness of the approach is illustrated by measured results from CMOS and BiCMOS technologies.

This paper presents a simple, physics-based and continuous model for the quantum effects and poly... more This paper presents a simple, physics-based and continuous model for the quantum effects and polydepletion in deep submicron MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from non-saturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicron technologies is provided showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice as well as efficient circuit simulation.

2015 International Conference on Noise and Fluctuations (ICNF), 2015

In this paper, a thorough statistical investigation of low frequency noise (LFN) variability in M... more In this paper, a thorough statistical investigation of low frequency noise (LFN) variability in MOSFETs is presented. In smaller-sized devices, noise fluctuations are areadominated. In moderate-to large-sized transistors (Area >> 1μm 2 ), normalized noise fluctuations are roughly independent of area, but show a distinct degradation towards weak inversion (subthreshold). A new model is proposed for the gatevoltage dependence of 1/f noise variations in moderately-sized transistors. We show that the gate-voltage dependence may be related to transconductance-to-current ratio g m /I D . Extensive measurements of low frequency noise variability in experimental 180nm CMOS confirm the newly proposed model.

The growing demand for WiMAX integrated circuits has motivated the system level analysis of a dir... more The growing demand for WiMAX integrated circuits has motivated the system level analysis of a direct-conversion receiver at 5.3 GHz and the corresponding mixer circuit design. The specifications set by the IEEE WirelessMAN 802.16 protocol are met. The corresponding mixer circuit is designed using MOSFETs in a 0.25μm SiGe BiCMOS technology. Inductive resonance technique is used to succeed optimum conversion

This paper presents the foundations that lead to the EKV MOS transistor compact model. It describ... more This paper presents the foundations that lead to the EKV MOS transistor compact model. It describes all the basic concepts required to derive the large-signal and small- signal charge-based model that is valid in all modes of in- version, from weak to strong inversion through moderate inversion. The general small-signal model valid in quasi- static and non-quasi-static operation is also

2006 13th IEEE International Conference on Electronics, Circuits and Systems, 2006

This paper presents a methodology for the design of a CMOS Low-Noise Amplifier (LNA) operating at... more This paper presents a methodology for the design of a CMOS Low-Noise Amplifier (LNA) operating at 5.5GHz. As an example, the design of a narrow-band cascode LNA intended for WiMax application in the frequency range from 5-6GHz is analyzed, using an 120nm CMOS technology. Trade-offs in the design, such as noise figure, gain, linearity are explored, based on the inversion coefficient and channel length of the MOS transistors. The design accounts for the effect of induced gate noise in the MOSFETs using the EKV3 model and accounts for non-ideal inductors. It is clearly shown how reduced channel length also leads to lower levels of inversion for best LNA performance.

Solid-State Electronics, 2015

The review of this paper was arranged by Prof. S. Cristoloveanu

Design of System on a Chip, 2004

In the design cycle of complex integrated circuits, the compact device simulation models are the ... more In the design cycle of complex integrated circuits, the compact device simulation models are the privileged vehicle of information between the foundry and the designer. Effective circuit design, particularly in the context of analog and mixed analog-digital circuits using silicon CMOS technology, requires a MOS transistor (MOST) circuit simulation model well adapted both to the technology and to the designer's needs. The MOST model itself should also help portable design, since design-reuse becomes a major advantage in the fast development of new products. Clearly, the MOST model must be based on sound physical concepts, and be parameterized in such a way that it allows easy adaptation to very different CMOS technologies, and provides the designer with information on important parameters for design. This chapter describes an analytical, scalable compact MOST model, called 'EKV' MOST model, which is built on fundamental physical properties of the MOS transistor. Among the original concepts used in this model are the normalization of the channel current, and taking the substrate as a reference instead of the source. The basic long-channel model is formulated in Chapter 3 symmetric terms of the source-to-bulk and drain-to-bulk voltages. In particular, the transconductance-to-current ratio is accurately described for all levels of current from weak inversion through moderate and to strong inversion. This characteristic is almost invariant with respect to process parameters and technology scaling; therefore, the model can be adjusted to a large range of different technologies. Short-channel effects have been included in the model for the simulation of deep submicron technologies. A full chargebased dynamic model as well as the thermal noise model are derived within the same approach. The continuity of the model characteristics is based on the use of a single equation, enhancing circuit convergence. The relative simplicity of the model and its low number of parameters also ease the process of parameter extraction, for which an original method is proposed. This MOST model is used in the context of low-voltage, low-current analog and analogdigital circuit design using deep submicron technologies. A version of this model based on the same fundamental concepts, is also available as a publicdomain model in various commercially available simulators.