Amit Mehrotra - Profile on Academia.edu (original) (raw)
Papers by Amit Mehrotra
Simulation and Modelling Techniques for Noise in Radio Frequency Integrated Circuits
... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carlo... more ... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carloni, Sriram Rajamani, Marco, Rajeev Murgai, Wilsin, Rizwan, Premal, Tanvi, Ashwin, Pramod just to name a few. Hiking was my favourite hobby and Gurmeet and ...
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down. we present can be extended [1] for the MNA (Modified Nodal Analysis) formulation (i.e., DAE formulation) given by d=dt qx + f x = 0. 2 After any small disturbance that does not persist, the system asymptotically settles back to the original limit cycle. See [2] for a precise definition of this stability notion.
IEEE Transactions on Circuits and Systems I-regular Papers, 2000
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the brute-force Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly.
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. We present a rigorous nonlinear analysis for phase noise in oscillators and reach the following conclusions: the power spectrum of an oscillator does not blow up at the carrier frequency as predicted by many previous analyses. Instead, the shape of the spectrum is a Lorentzian (the shape of the squared magnitude of a one-pole lowpass filter transfer function) about each harmonic. The average spread (variance) of the timing jitter grows exactly linearly with time. A single scalar constant suffices to characterise both the timing jitter and spectral broadening due to phase noise. Previous linear analyses of phase noise make unphysical predictions such as infinite noise power. We develop efficient computational methods in the time and frequency domains for predicting phase noise. Our techniques are practical for large circuits. We obtain good matches between spectra predicted using our technique and measured results, even at frequencies close to the carrier and its harmonics, where most previous techniques break down
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down. we present can be extended [1] for the MNA (Modified Nodal Analysis) formulation (i.e., DAE formulation) given by d=dt qx + f x = 0. 2 After any small disturbance that does not persist, the system asymptotically settles back to the original limit cycle. See [2] for a precise definition of this stability notion.
ibstract Continuous scaling of VLSI circuits is reducing gate delays but rapidly ncreasing interc... more ibstract Continuous scaling of VLSI circuits is reducing gate delays but rapidly ncreasing interconnect delays. Semiconductor Industry Association (SIA) uadmap predicts that, beyond the 130 nm technology node, performance mprovement of advanced VLSI is likely to begin to saturate unless a paradigm .hift from present IC architecture is introduced.
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance... more This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micr... more We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that onchip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design.
IEEE Transactions on Electron Devices, 2001
This paper addresses the problem of power dissipation during the buffer insertion phase of interc... more This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal eff... more In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. This paper presents for the first time a rigorous coupled analysis of AC electromigration that are prevalent in signal lines and thermal effects arising due to Joule heating of the wires. The analysis is applied to study the effect of technology scaling using ITRS data, wherein the effects of increasing interconnect (Cu) resistivity with line dimensions and the effect of a finite barrier metal thickness have been included. Finally, we have also quantified the reliability implications for minimum sized vias in optimally buffered signal nets. Our analysis suggests that for the optimally buffered interconnects, while the maximum current density in the line remains limited by the performance, the current density in the vias exceeds the reliability limits and therefore requires careful consideration in the physical design process flow.
This paper presents a methodology for quantitative analysis of the role of electromigration (EM) ... more This paper presents a methodology for quantitative analysis of the role of electromigration (EM) reliability and interconnect performance in determining the optimal interconnect design in low-WCu interconnect systems. It is demonstrated that EM design limits for signal lines are satisfied once interconnect performance is optimized.
Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology. Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with particular regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS). Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects.
Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies
This paper introduces the idea of electrothermally coupled evaluation of junction temperature to ... more This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.
IEEE Transactions on Electron Devices, 2004
This paper addresses the critical problem of global wire optimization for nanometer scale very la... more This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes.
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die t... more Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (V dd ) and threshold (V th ) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the V dd -V th plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.
Power dissipation issues in interconnect performance optimization for sub-180 nm designs
... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanf... more ... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanford CA 94305 kaustav@ee.stanfard.edu Abstract ... The delay of an optimally buffered line is linear in its length [3]. However, for large high-performance de-signs. ...
This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM tech... more This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.
This paper presents a comprehensive analysis of the themal effects in advanced high performance i... more This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated.
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects
... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@s... more ... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@stanford.edu ... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice ...
Simulation and Modelling Techniques for Noise in Radio Frequency Integrated Circuits
... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carlo... more ... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carloni, Sriram Rajamani, Marco, Rajeev Murgai, Wilsin, Rizwan, Premal, Tanvi, Ashwin, Pramod just to name a few. Hiking was my favourite hobby and Gurmeet and ...
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down. we present can be extended [1] for the MNA (Modified Nodal Analysis) formulation (i.e., DAE formulation) given by d=dt qx + f x = 0. 2 After any small disturbance that does not persist, the system asymptotically settles back to the original limit cycle. See [2] for a precise definition of this stability notion.
IEEE Transactions on Circuits and Systems I-regular Papers, 2000
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the brute-force Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly.
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. We present a rigorous nonlinear analysis for phase noise in oscillators and reach the following conclusions: the power spectrum of an oscillator does not blow up at the carrier frequency as predicted by many previous analyses. Instead, the shape of the spectrum is a Lorentzian (the shape of the squared magnitude of a one-pole lowpass filter transfer function) about each harmonic. The average spread (variance) of the timing jitter grows exactly linearly with time. A single scalar constant suffices to characterise both the timing jitter and spectral broadening due to phase noise. Previous linear analyses of phase noise make unphysical predictions such as infinite noise power. We develop efficient computational methods in the time and frequency domains for predicting phase noise. Our techniques are practical for large circuits. We obtain good matches between spectra predicted using our technique and measured results, even at frequencies close to the carrier and its harmonics, where most previous techniques break down
Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down. we present can be extended [1] for the MNA (Modified Nodal Analysis) formulation (i.e., DAE formulation) given by d=dt qx + f x = 0. 2 After any small disturbance that does not persist, the system asymptotically settles back to the original limit cycle. See [2] for a precise definition of this stability notion.
ibstract Continuous scaling of VLSI circuits is reducing gate delays but rapidly ncreasing interc... more ibstract Continuous scaling of VLSI circuits is reducing gate delays but rapidly ncreasing interconnect delays. Semiconductor Industry Association (SIA) uadmap predicts that, beyond the 130 nm technology node, performance mprovement of advanced VLSI is likely to begin to saturate unless a paradigm .hift from present IC architecture is introduced.
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance... more This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start dominating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], interconnects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, interconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling.
We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micr... more We propose a new VLSI layout methodology which addresses the main problems faced in Deep Sub-Micron (DSM) integrated circuit design. Our layout "fabric" scheme eliminates the conventional notion of power and ground routing on the integrated circuit die. Instead, power and ground are essentially "pre-routed" all over the die. By a clever arrangement of power/ground and signal pins, we almost completely eliminate the capacitive effects between signal wires. Additionally, we get a power and ground distribution network with a very low resistance at any point on the die. Another advantage of our scheme is that the arrangement of conductors ensures that onchip inductances are uniformly negligible. Finally, characterization of the circuit delays, capacitances and resistances becomes extremely simple in our scheme, and needs to be done only once for a design.
IEEE Transactions on Electron Devices, 2001
This paper addresses the problem of power dissipation during the buffer insertion phase of interc... more This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.
In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal eff... more In deep submicron VLSI circuits, interconnect reliability due to electromigration and thermal effects is fast becoming a serious design issue particularly for long signal lines. This paper presents for the first time a rigorous coupled analysis of AC electromigration that are prevalent in signal lines and thermal effects arising due to Joule heating of the wires. The analysis is applied to study the effect of technology scaling using ITRS data, wherein the effects of increasing interconnect (Cu) resistivity with line dimensions and the effect of a finite barrier metal thickness have been included. Finally, we have also quantified the reliability implications for minimum sized vias in optimally buffered signal nets. Our analysis suggests that for the optimally buffered interconnects, while the maximum current density in the line remains limited by the performance, the current density in the vias exceeds the reliability limits and therefore requires careful consideration in the physical design process flow.
This paper presents a methodology for quantitative analysis of the role of electromigration (EM) ... more This paper presents a methodology for quantitative analysis of the role of electromigration (EM) reliability and interconnect performance in determining the optimal interconnect design in low-WCu interconnect systems. It is demonstrated that EM design limits for signal lines are satisfied once interconnect performance is optimized.
Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology. Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with particular regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS). Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects.
Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies
This paper introduces the idea of electrothermally coupled evaluation of junction temperature to ... more This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines.
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.
IEEE Transactions on Electron Devices, 2004
This paper addresses the critical problem of global wire optimization for nanometer scale very la... more This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes.
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die t... more Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (V dd ) and threshold (V th ) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the V dd -V th plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.
Power dissipation issues in interconnect performance optimization for sub-180 nm designs
... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanf... more ... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanford CA 94305 kaustav@ee.stanfard.edu Abstract ... The delay of an optimally buffered line is linear in its length [3]. However, for large high-performance de-signs. ...
This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM tech... more This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.
This paper presents a comprehensive analysis of the themal effects in advanced high performance i... more This paper presents a comprehensive analysis of the themal effects in advanced high performance interconnect systems arising due to selfheating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upperlevel signal lines are investigated.
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects
... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@s... more ... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@stanford.edu ... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice ...