Amit Mehrotra - Academia.edu (original) (raw)
Papers by Amit Mehrotra
... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carlo... more ... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carloni, Sriram Rajamani, Marco, Rajeev Murgai, Wilsin, Rizwan, Premal, Tanvi, Ashwin, Pramod just to name a few. Hiking was my favourite hobby and Gurmeet and ...
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IEEE Transactions on Circuits and Systems I-regular Papers, 2000
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Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. We present a rigorous nonlinear analysis for phase noise in oscillators and reach the following conclusions: the power spectrum of an oscillator does not blow up at the carrier frequency as predicted by many previous analyses. Instead, the shape of the spectrum is a Lorentzian (the shape of the squared magnitude of a one-pole lowpass filter transfer function) about each harmonic. The average spread (variance) of the timing jitter grows exactly linearly with time. A single scalar constant suffices to characterise both the timing jitter and spectral broadening due to phase noise. Previous linear analyses of phase noise make unphysical predictions such as infinite noise power. We develop efficient computational methods in the time and frequency domains for predicting phase noise. Our techniques are practical for large circuits. We obtain good matches between spectra predicted using our technique and measured results, even at frequencies close to the carrier and its harmonics, where most previous techniques break down
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IEEE Transactions on Electron Devices, 2001
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This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology. Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with particular regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS). Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects.
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This paper introduces the idea of electrothermally coupled evaluation of junction temperature to ... more This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines.
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IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.
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IEEE Transactions on Electron Devices, 2004
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... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanf... more ... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanford CA 94305 kaustav@ee.stanfard.edu Abstract ... The delay of an optimally buffered line is linear in its length [3]. However, for large high-performance de-signs. ...
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... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@s... more ... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@stanford.edu ... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice ...
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... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carlo... more ... undergraduate days. Berkeley gave me chance to make new friends: Kaustav, Gurmeet, Luca Carloni, Sriram Rajamani, Marco, Rajeev Murgai, Wilsin, Rizwan, Premal, Tanvi, Ashwin, Pramod just to name a few. Hiking was my favourite hobby and Gurmeet and ...
Bookmarks Related papers MentionsView impact
Bookmarks Related papers MentionsView impact
IEEE Transactions on Circuits and Systems I-regular Papers, 2000
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Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as i... more Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. We present a rigorous nonlinear analysis for phase noise in oscillators and reach the following conclusions: the power spectrum of an oscillator does not blow up at the carrier frequency as predicted by many previous analyses. Instead, the shape of the spectrum is a Lorentzian (the shape of the squared magnitude of a one-pole lowpass filter transfer function) about each harmonic. The average spread (variance) of the timing jitter grows exactly linearly with time. A single scalar constant suffices to characterise both the timing jitter and spectral broadening due to phase noise. Previous linear analyses of phase noise make unphysical predictions such as infinite noise power. We develop efficient computational methods in the time and frequency domains for predicting phase noise. Our techniques are practical for large circuits. We obtain good matches between spectra predicted using our technique and measured results, even at frequencies close to the carrier and its harmonics, where most previous techniques break down
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IEEE Transactions on Electron Devices, 2001
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This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Furthermore, an optimal repeater insertion scheme for distributed RLC interconnects is also presented using a novel performance optimization methodology. Additionally, the impact of line inductance on interconnect performance has been analyzed in detail with particular regards to technology scaling based on the International Technology Roadmap for Semiconductors (ITRS). Contrary to conventional wisdom, it is shown that the effect of line inductance on optimized interconnect performance will actually diminish for scaled global interconnects.
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This paper introduces the idea of electrothermally coupled evaluation of junction temperature to ... more This paper introduces the idea of electrothermally coupled evaluation of junction temperature to accurately estimate the lifetime of interconnects under electromigration (EM) constraints in leakage dominant technologies. The junction temperature thus evaluated with our proposed methodology is incorporated into the interconnect temperature-rise equation (which includes Joule-heating) and is solved self-consistently with both unipolar and bipolar EM lifetime equations to estimate accurate interconnect metal temperature and to provide comprehensive design guidelines for maximum allowable current density in power/ground and signal lines.
Bookmarks Related papers MentionsView impact
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2002
This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC inte... more This paper introduces an accurate analysis of on-chip inductance effects for distributed RLC interconnects that takes the effect of both the series resistance and the output parasitic capacitance of the driver into account. Using rigorous first principle calculations, accurate expressions for the transfer function of these lines and their time-domain response have been presented for the first time. Using these, a new and computationally efficient performance optimization techniques for distributed RLC interconnects has been introduced. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behavior and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in driver output resistance and input capacitance with scaling can make deep submicron designs increasingly susceptible to inductance effects if global interconnects are not scaled. For scaled global interconnects with increasing line resistance per unit length, as prescribed by the International Technology Roadmap for Semiconductors, the effect of inductance on interconnect performance actually diminishes.
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IEEE Transactions on Electron Devices, 2004
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... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanf... more ... Stanford University Coordinated Science Lab. University of Illinois at Urbana-Champaign Stanford CA 94305 kaustav@ee.stanfard.edu Abstract ... The delay of an optimally buffered line is linear in its length [3]. However, for large high-performance de-signs. ...
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Bookmarks Related papers MentionsView impact
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... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@s... more ... Kaustav Banerjee Center for Integrated Systems Stanford University Stanford CA 94305kaustav@stanford.edu ... personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice ...
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