Mircea Bodea - Academia.edu (original) (raw)
Papers by Mircea Bodea
2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010
Using symbolic algorithms for small signal circuit parameter extraction could make possible imple... more Using symbolic algorithms for small signal circuit parameter extraction could make possible implementing extraction programs which, unlike those based on pure numerical methods, no longer require initial (“start”) values for the parameters being extracted, thus ensuring that the final result corresponds to the true global minimum of the error function. Solving the extraction problem, in the particular case of a
2008 11th International Conference on Optimization of Electrical and Electronic Equipment, 2008
A direct extraction method for small signal parameter extraction of a linear circuit is presented... more A direct extraction method for small signal parameter extraction of a linear circuit is presented. Unlike the numerical method approach, this algorithm doesn't make use of "start values" and performs complex symbolic computation in conjunction with numeric subroutines. Extraction of small signal parameters of a particular circuit illustrates the viability of the method and evidences the elements of the associated
1976 International Electron Devices Meeting, 1976
ABSTRACT
Electronics Letters, 1980
ABSTRACT
Electronics Letters, 1976
ABSTRACT
A full thermal investigation of the 726-microampere Temperature Stabilized Substrate Integrated C... more A full thermal investigation of the 726-microampere Temperature Stabilized Substrate Integrated Circuit (TSS IC) has been performed using a new and accurate quasi-three-dimensional numerical method. This new method allows a reduction of the three-dimensional thermal problem to a bidimensional one. This reduction does not affect the accuracy of the computed temperature distribution of the semiconductor chip. The validity of our
UPB Scientific Bulletin, Series C: Electrical Engineering
Problema matematică asociată problemei de extracţie a parametrilor unui circuit se reduce la dete... more Problema matematică asociată problemei de extracţie a parametrilor unui circuit se reduce la determinarea minimului global al unei funcţii obiectiv obţinută prin metoda celor mai mici pătrate. În cazul analizei de semnal mic a unui circuit (când se utilizează un model liniar), funcţia asociată circuitului este o funcţie raţională, şi în consecinţă şi funcţia obiectiv are aceeaşi formă. Aceasta permite a se lua în considerare rezolvarea sistemului de ecuaţii format cu derivatele parţiale ale funcţiei obiectiv pentru determinarea, în final, a minimului global, metoda care, spre deosebire de metoda pur numerică, nu mai necesită valori "de start" ale parametrilor de extras şi în plus garantează faptul ca rezultatul obţinut corespunde minimului global. Această abordare conduce la problema matematică a rezolvării unui sistem de ecuaţii format cu funcţii raţionale, care poate fi transformat într-un sistem polinomial echivalent. În lucrare se determină modul în care numărul de valori măsurate ale unei funcţii de semnal mic (asociată unui circuit liniar), care se iau în considerare, influenţează gradul acestui sistem iniţial de ecuaţii polinomiale. Se arată faptul că timpul de calcul total, (care depinde de gradul sistemului iniţial de ecuaţii polinomiale şi, de asemenea, de algoritmul de reducere a sistemului polinomial la un sistem echivalent quasi triangular, rezolvabil prin metode numerice) poate fi controlat prin ajustarea acestui număr. Utilizând această proprietate/dependenţă, care permite generarea de probleme matematice (sisteme de ecuaţii polinomiale iniţiale) de complexităţi diferite, pentru aceeaşi problemă de extracţie, se analizează în cazul unui circuit particular, posibilitatea obţinerii unui rezultat într-un timp rezonabil, cu algoritmii incluşi în două sisteme CAD pentru matematică. Concluziile identifică oportunitatea utilizării fiecăruia dintre aceste instrumente matematice, pentru implementarea unui program de extracţie nu neapărat bazat pe un sistem CAD.
Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte ... more Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte proiectarea sintetizoarelor de frecvenţă utilizate în transiverele reconfigurabile de bandă largă, urmărind identificarea unei arhitecturi optime pentru sintetizatorul de frecvenţă, ţinând cont de particularităţile proiectării de radiofrecvenţă. Lucrarea descrie şi analizează principalele surse de zgomot din circuit şi construieşte un model în baza căruia performanţele de zgomot ale sintetizorului pot fi simulate cunoscându-se contribuţiile individuale ale subblocurilor componente. În urma acestei analize, este dezvoltată o nouă arhitectură a sintetizorului de frecvenţă ce implementează două filtre trece jos, unul extern, ce optimizează zgomotul de fază, şi unul intern, de dimensiuni reduse, ce optimizează aria şi consumul de putere. This paper presents the phase noise and area -power consumption trade-off defining the frequency synthesizers used in Software Defined Radio Transceivers (SDR), focused on finding the optimum frequency synthesizer architecture, given the wide-band RF design specifics. The paper describes and analyses the major noise sources of the circuit and builds a model used is simulating the synthesizer's noise performance. Based on the analysis, a new architecture for the SDR frequency synthesizer is proposed. The proposed synthesizer implements two loop filters: an external one, optimizing the phase noise performance, and an internal one of reduced size, optimizing area and power consumption.
In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm inte... more In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, V DC =1 V, P out =0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground inductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power control capabilities and highlight linearization methods.
This paper develops an analytical model for a standard topology, fully differential, switched cap... more This paper develops an analytical model for a standard topology, fully differential, switched capacitor amplifier; including the base amplifier offset voltage and common mode range, and capacitor mismatch effects. The amplifier is designed in a 0.6 µm process and the analytical model accuracy is compared with the simulation results.
Această lucrare prezintă: (1) o trecere în revistă comparativă a trei topologii tipce pentru etaj... more Această lucrare prezintă: (1) o trecere în revistă comparativă a trei topologii tipce pentru etajele de intrare CMOS "rail-to-rail" (RRIS): un etaj simplu, un etaj cu transconductanţă constantă şi un etaj care funcţionează în regim de inversie slabă, (2) implementarea etajului de sumare şi (3) influenţa celor trei topologii asupra etajului de sumare. Circuitele prezentate sunt implementate într-o tehnologie CMOS standard de 0.8 μm. Performanţele etajelor au fost determinate prin analiză manuală iar rezultatele au fost verificate prin simulare SPICE This paper presents (1) a comparative overview for three widely used CMOS rail-to-rail input stage (RRIS) topologies: a simple stage, a constant transconductance stage, and a weak inversion RRIS stage, (2) the summing stage implementation, and (3) the three RRIS topologies influence on the summing stage. The described circuits have been implemented in a standard 0.8 μm CMOS process. The stages performances were determined by means of manual analysis and the results were checked by SPICE analysis.
Revue Roumaine des Sciences Techniques - Serie Électrotechnique et Énergétique
This paper presents the analysis of CMOS re-configurable multi-standard radio receivers building ... more This paper presents the analysis of CMOS re-configurable multi-standard radio receivers building blocks core. The paper's main goal is to determine the building blocks key parameters, like gain, noise figure (NF) and third order intercept point (IP3) and to link them to the receiver overall performance. An overview of existing circuit topologies is presented. The analysis emphasizes the solutions that fit best a true re-configurable multi-standard implementation.
This paper analyzes the noise–linearity breakdown in direct conversion multi-standard radio recei... more This paper analyzes the noise–linearity breakdown in direct conversion multi-standard radio receivers embedding analog signal conditioning. The paper’s main goal is to develop a systematic noise–linearity partitioning methodology to be used in splitting the multi-standard receiver noise and linearity budget between its high frequency (HF) part and its low frequency (LF) baseband part. To this aim, a new and efficient design methodology tailored towards multi-standard receivers, and based on manual analysis, is developed. By using the developed methodology, power saving is enabled in the HF part through changing the multi-standard receiver HF part noise and linearity performance with its RF front-end gain. While for the LF part, the analysis revealed the performance can be kept the same to allow power optimization through dedicated circuit design.
This paper analyses the key trade-off that shapes the design of direct conversion radio receivers... more This paper analyses the key trade-off that shapes the design of direct conversion radio receivers embedding analog signal conditioning: the trade-off between the receiver area, determined by its anti-alias Low Pass Filter (LPF) order, and its power consumption, constrained by the ADC specifications of resolution and speed. The paper's main goal is to determine the receiver's LPF order that enables the complete analog channel selection in the context of a multi-standard receiver implementation. Based on the multi-standard receiver generic blocker diagram analysis, a first order, system level analysis is used to determine the LPF order. The analysis is constructed from the circuit / transistor level designer perspective and is also used for estimating the impact of the complete analog channel selection on the receiver RF front-end power consumption and area. Thus, by using this analysis methodology the designer is enabled to handle efficiently the large amount of information r...
Revue Roumaine des Sciences Techniques - Serie Électrotechnique et Énergétique
This paper presents the analysis of CMOS re-configurable multi-standard radio receiv¬ers building... more This paper presents the analysis of CMOS re-configurable multi-standard radio receiv¬ers building blocks core. The paper’s main goal is to determine the building blocks key parameters, like gain, noise figure (NF) and third order intercept point (IP3) and to link them to the receiver overall performance. An overview of existing circuit topologies is presented. The analysis emphasizes the solutions that fit best a true re-configurable multi-standard implementation.
This paper analyzes the gain – noise – linearity partitioning in multi-standard radio receivers e... more This paper analyzes the gain – noise – linearity partitioning in multi-standard radio receivers embedding baseband analog signal conditioning. The presented novel gain partitioning strategy tailored towards multi-standard radio receivers optimally mitigates the extreme reception conditions specific to the wireless environment. Based on a first order system level analysis, the paper develops a standard independent methodology that drives the gain partitioning strategy and enables the designer to handle efficiently the large amount of information from the envisaged wireless standards. The receiver gain is split between an RF front-end embedding programmable gain and a high-dynamic range Variable Gain Amplifier (VGA). As the receiver NF and IIP3 change with the RF front-end gain, we proposed a generic algorithm to find the optimal gain partitioning between the receiver's two variable gain blocks.
2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003
This paper evaluates the design trade-offs for a high frequency RF front-end. The main three fact... more This paper evaluates the design trade-offs for a high frequency RF front-end. The main three factors - gain, linearity, noise - influence is analyzed, in order to get an optimum performance for the receiver. The analysis is focused on the weight of the main blocks (the low noise amplifier - LNA and the mixer) parameters oil the RF frontend operation.
2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003
This paper presents a simple and efficient tool for fast evaluation of high performance BiCMOS RF... more This paper presents a simple and efficient tool for fast evaluation of high performance BiCMOS RF process transistors. From the manual circuit analysis and design point of view the huge amount of information regarding transistors used in RF IC design tends to obscure the basic design parameters and theirs dependence on bias and lay-out details. Therefore it is worth and rewarding to build up a dedicated "tool" that helps the designer to evaluate "on the spot" some key electrical data sheets parameters. The "tool" consists of an evaluation circuit that allows setting the desired values for the transistors under test both static and dynamic operation parameters. This "tool" assists the designer in choosing the appropriate transistor for a given application.
2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), 2010
Using symbolic algorithms for small signal circuit parameter extraction could make possible imple... more Using symbolic algorithms for small signal circuit parameter extraction could make possible implementing extraction programs which, unlike those based on pure numerical methods, no longer require initial (“start”) values for the parameters being extracted, thus ensuring that the final result corresponds to the true global minimum of the error function. Solving the extraction problem, in the particular case of a
2008 11th International Conference on Optimization of Electrical and Electronic Equipment, 2008
A direct extraction method for small signal parameter extraction of a linear circuit is presented... more A direct extraction method for small signal parameter extraction of a linear circuit is presented. Unlike the numerical method approach, this algorithm doesn't make use of "start values" and performs complex symbolic computation in conjunction with numeric subroutines. Extraction of small signal parameters of a particular circuit illustrates the viability of the method and evidences the elements of the associated
1976 International Electron Devices Meeting, 1976
ABSTRACT
Electronics Letters, 1980
ABSTRACT
Electronics Letters, 1976
ABSTRACT
A full thermal investigation of the 726-microampere Temperature Stabilized Substrate Integrated C... more A full thermal investigation of the 726-microampere Temperature Stabilized Substrate Integrated Circuit (TSS IC) has been performed using a new and accurate quasi-three-dimensional numerical method. This new method allows a reduction of the three-dimensional thermal problem to a bidimensional one. This reduction does not affect the accuracy of the computed temperature distribution of the semiconductor chip. The validity of our
UPB Scientific Bulletin, Series C: Electrical Engineering
Problema matematică asociată problemei de extracţie a parametrilor unui circuit se reduce la dete... more Problema matematică asociată problemei de extracţie a parametrilor unui circuit se reduce la determinarea minimului global al unei funcţii obiectiv obţinută prin metoda celor mai mici pătrate. În cazul analizei de semnal mic a unui circuit (când se utilizează un model liniar), funcţia asociată circuitului este o funcţie raţională, şi în consecinţă şi funcţia obiectiv are aceeaşi formă. Aceasta permite a se lua în considerare rezolvarea sistemului de ecuaţii format cu derivatele parţiale ale funcţiei obiectiv pentru determinarea, în final, a minimului global, metoda care, spre deosebire de metoda pur numerică, nu mai necesită valori "de start" ale parametrilor de extras şi în plus garantează faptul ca rezultatul obţinut corespunde minimului global. Această abordare conduce la problema matematică a rezolvării unui sistem de ecuaţii format cu funcţii raţionale, care poate fi transformat într-un sistem polinomial echivalent. În lucrare se determină modul în care numărul de valori măsurate ale unei funcţii de semnal mic (asociată unui circuit liniar), care se iau în considerare, influenţează gradul acestui sistem iniţial de ecuaţii polinomiale. Se arată faptul că timpul de calcul total, (care depinde de gradul sistemului iniţial de ecuaţii polinomiale şi, de asemenea, de algoritmul de reducere a sistemului polinomial la un sistem echivalent quasi triangular, rezolvabil prin metode numerice) poate fi controlat prin ajustarea acestui număr. Utilizând această proprietate/dependenţă, care permite generarea de probleme matematice (sisteme de ecuaţii polinomiale iniţiale) de complexităţi diferite, pentru aceeaşi problemă de extracţie, se analizează în cazul unui circuit particular, posibilitatea obţinerii unui rezultat într-un timp rezonabil, cu algoritmii incluşi în două sisteme CAD pentru matematică. Concluziile identifică oportunitatea utilizării fiecăruia dintre aceste instrumente matematice, pentru implementarea unui program de extracţie nu neapărat bazat pe un sistem CAD.
Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte ... more Lucrarea analizează compromisul dintre zgomotul de fază, aria şi consumul de putere ce defineşte proiectarea sintetizoarelor de frecvenţă utilizate în transiverele reconfigurabile de bandă largă, urmărind identificarea unei arhitecturi optime pentru sintetizatorul de frecvenţă, ţinând cont de particularităţile proiectării de radiofrecvenţă. Lucrarea descrie şi analizează principalele surse de zgomot din circuit şi construieşte un model în baza căruia performanţele de zgomot ale sintetizorului pot fi simulate cunoscându-se contribuţiile individuale ale subblocurilor componente. În urma acestei analize, este dezvoltată o nouă arhitectură a sintetizorului de frecvenţă ce implementează două filtre trece jos, unul extern, ce optimizează zgomotul de fază, şi unul intern, de dimensiuni reduse, ce optimizează aria şi consumul de putere. This paper presents the phase noise and area -power consumption trade-off defining the frequency synthesizers used in Software Defined Radio Transceivers (SDR), focused on finding the optimum frequency synthesizer architecture, given the wide-band RF design specifics. The paper describes and analyses the major noise sources of the circuit and builds a model used is simulating the synthesizer's noise performance. Based on the analysis, a new architecture for the SDR frequency synthesizer is proposed. The proposed synthesizer implements two loop filters: an external one, optimizing the phase noise performance, and an internal one of reduced size, optimizing area and power consumption.
In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm inte... more In this paper we design a low-voltage class-E power amplifier (PA) in a standard CMOS 0.35µm integrated technology, to be used in a UMTS transceiver having the following specifications: f=1.95 GHz, V DC =1 V, P out =0.5 W. The designed class-E network accommodates the simultaneous presence of a parasitic ground inductance and losses in the switch and shunt-capacitor. The transistor is dimensioned for an optimum PAE (power added efficiency). Finally, we simulate the power control capabilities and highlight linearization methods.
This paper develops an analytical model for a standard topology, fully differential, switched cap... more This paper develops an analytical model for a standard topology, fully differential, switched capacitor amplifier; including the base amplifier offset voltage and common mode range, and capacitor mismatch effects. The amplifier is designed in a 0.6 µm process and the analytical model accuracy is compared with the simulation results.
Această lucrare prezintă: (1) o trecere în revistă comparativă a trei topologii tipce pentru etaj... more Această lucrare prezintă: (1) o trecere în revistă comparativă a trei topologii tipce pentru etajele de intrare CMOS "rail-to-rail" (RRIS): un etaj simplu, un etaj cu transconductanţă constantă şi un etaj care funcţionează în regim de inversie slabă, (2) implementarea etajului de sumare şi (3) influenţa celor trei topologii asupra etajului de sumare. Circuitele prezentate sunt implementate într-o tehnologie CMOS standard de 0.8 μm. Performanţele etajelor au fost determinate prin analiză manuală iar rezultatele au fost verificate prin simulare SPICE This paper presents (1) a comparative overview for three widely used CMOS rail-to-rail input stage (RRIS) topologies: a simple stage, a constant transconductance stage, and a weak inversion RRIS stage, (2) the summing stage implementation, and (3) the three RRIS topologies influence on the summing stage. The described circuits have been implemented in a standard 0.8 μm CMOS process. The stages performances were determined by means of manual analysis and the results were checked by SPICE analysis.
Revue Roumaine des Sciences Techniques - Serie Électrotechnique et Énergétique
This paper presents the analysis of CMOS re-configurable multi-standard radio receivers building ... more This paper presents the analysis of CMOS re-configurable multi-standard radio receivers building blocks core. The paper's main goal is to determine the building blocks key parameters, like gain, noise figure (NF) and third order intercept point (IP3) and to link them to the receiver overall performance. An overview of existing circuit topologies is presented. The analysis emphasizes the solutions that fit best a true re-configurable multi-standard implementation.
This paper analyzes the noise–linearity breakdown in direct conversion multi-standard radio recei... more This paper analyzes the noise–linearity breakdown in direct conversion multi-standard radio receivers embedding analog signal conditioning. The paper’s main goal is to develop a systematic noise–linearity partitioning methodology to be used in splitting the multi-standard receiver noise and linearity budget between its high frequency (HF) part and its low frequency (LF) baseband part. To this aim, a new and efficient design methodology tailored towards multi-standard receivers, and based on manual analysis, is developed. By using the developed methodology, power saving is enabled in the HF part through changing the multi-standard receiver HF part noise and linearity performance with its RF front-end gain. While for the LF part, the analysis revealed the performance can be kept the same to allow power optimization through dedicated circuit design.
This paper analyses the key trade-off that shapes the design of direct conversion radio receivers... more This paper analyses the key trade-off that shapes the design of direct conversion radio receivers embedding analog signal conditioning: the trade-off between the receiver area, determined by its anti-alias Low Pass Filter (LPF) order, and its power consumption, constrained by the ADC specifications of resolution and speed. The paper's main goal is to determine the receiver's LPF order that enables the complete analog channel selection in the context of a multi-standard receiver implementation. Based on the multi-standard receiver generic blocker diagram analysis, a first order, system level analysis is used to determine the LPF order. The analysis is constructed from the circuit / transistor level designer perspective and is also used for estimating the impact of the complete analog channel selection on the receiver RF front-end power consumption and area. Thus, by using this analysis methodology the designer is enabled to handle efficiently the large amount of information r...
Revue Roumaine des Sciences Techniques - Serie Électrotechnique et Énergétique
This paper presents the analysis of CMOS re-configurable multi-standard radio receiv¬ers building... more This paper presents the analysis of CMOS re-configurable multi-standard radio receiv¬ers building blocks core. The paper’s main goal is to determine the building blocks key parameters, like gain, noise figure (NF) and third order intercept point (IP3) and to link them to the receiver overall performance. An overview of existing circuit topologies is presented. The analysis emphasizes the solutions that fit best a true re-configurable multi-standard implementation.
This paper analyzes the gain – noise – linearity partitioning in multi-standard radio receivers e... more This paper analyzes the gain – noise – linearity partitioning in multi-standard radio receivers embedding baseband analog signal conditioning. The presented novel gain partitioning strategy tailored towards multi-standard radio receivers optimally mitigates the extreme reception conditions specific to the wireless environment. Based on a first order system level analysis, the paper develops a standard independent methodology that drives the gain partitioning strategy and enables the designer to handle efficiently the large amount of information from the envisaged wireless standards. The receiver gain is split between an RF front-end embedding programmable gain and a high-dynamic range Variable Gain Amplifier (VGA). As the receiver NF and IIP3 change with the RF front-end gain, we proposed a generic algorithm to find the optimal gain partitioning between the receiver's two variable gain blocks.
2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003
This paper evaluates the design trade-offs for a high frequency RF front-end. The main three fact... more This paper evaluates the design trade-offs for a high frequency RF front-end. The main three factors - gain, linearity, noise - influence is analyzed, in order to get an optimum performance for the receiver. The analysis is focused on the weight of the main blocks (the low noise amplifier - LNA and the mixer) parameters oil the RF frontend operation.
2003 International Semiconductor Conference. CAS 2003 Proceedings (IEEE Cat. No.03TH8676), 2003
This paper presents a simple and efficient tool for fast evaluation of high performance BiCMOS RF... more This paper presents a simple and efficient tool for fast evaluation of high performance BiCMOS RF process transistors. From the manual circuit analysis and design point of view the huge amount of information regarding transistors used in RF IC design tends to obscure the basic design parameters and theirs dependence on bias and lay-out details. Therefore it is worth and rewarding to build up a dedicated "tool" that helps the designer to evaluate "on the spot" some key electrical data sheets parameters. The "tool" consists of an evaluation circuit that allows setting the desired values for the transistors under test both static and dynamic operation parameters. This "tool" assists the designer in choosing the appropriate transistor for a given application.