Jae-Woong Nah - Academia.edu (original) (raw)
Papers by Jae-Woong Nah
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
We developed a tool of molten solder injection which is able to form solder bumping on wafers, ce... more We developed a tool of molten solder injection which is able to form solder bumping on wafers, ceramic/organic substrates, flexible circuits, and Si via filling from fine pitch to large pitch. One tool has capabilities of solder bumping on wafers from 15 microns diameter to larger than 1000 microns diameter, bumping on organic substrates from flip chip pre-solder to BGA size, soldering on flexible circuits with < 25 microns width of circle and square shape, and via filling of Si wafer with various via diameters. Also, this tool enables the change of solder composition to be very easy and fast because simple switch of the solder injection head allows to change the solder composition like switching an ink cartridge in an inkjet printer. The solder injection tool head contains a reservoir of molten solder of desired composition and a slot through which the molten solder is injected with an optimized combination of pressure and temperature. The solder injection slot of the head is configured in the portion of compliant material and low friction material such that this combination provides good wiping characteristics as well as allowing the IMS head to better track surface topography of an organic substrate. This paper will review key attributes of the molten solder injection tool and discuss differences in the processes required for each different applications of solder bumping on Si wafers and ceramic/organic/flexible substrates as well as filling solder into Si vias. We will describe data of 200mm wafer bumping results with different bump diameters and shape, solder bumping results on organic and ceramic substrates, soldering on flexible circuits, and via filling results of Si. Also, solder alloy flexibility of this technology has been demonstrated from low melting temperature Pb-free solders to high melting temperature Pb-free solders.
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
This paper proposed a high-speed precision handling technology of micro-chip using programmable l... more This paper proposed a high-speed precision handling technology of micro-chip using programmable laser debonding technology for fan-out wafer level packaging (FOWLP) application, and investigated the programmable capability, the speed and the accuracy with laser debonding experiments on chips down to 25umX25um. The proposed FOWLP approach has features of: (a) all steps are based on wafer-level processes by using programmable laser debonding technology to achieve the reconstituted wafer, enabling high-speed precision hanldinghandling technology for micro-chip. And, (b) two bonding interface layers, one high-strength adhesive layer for chips firmly joined to handler and the other UV-sensitive layer for easily laser debonding, can improve the die-shift issues. The successfully debonding results, including selectively debonding 200umX400um chips from handler wafer and specifically debonding 25umX25um chips forming the letters "IBM", indicates the programmable capability of this...
Verfahren zum Bereitstellen eines Matrixmaterials zwischen einem gebunden Paar von Substraten, wo... more Verfahren zum Bereitstellen eines Matrixmaterials zwischen einem gebunden Paar von Substraten, wobei eine homogene Verteilung von anisotropen Fullermaterialien bereitgestellt ist. Funktionalisierte anisotrope Fullerpartikel sind gleichmasig mit einem Matrixmaterial gemischt, um eine homogene Mischung auszubilden. Ein gebundener Aufbau eines ersten Substrats und eines zweiten Substrats mit einer Anordnung von elektrischen Verbindungsaufbauten ist innerhalb einer Vakuumumgebung platziert. Die homogene Mischung des Matrixmaterials und der anisotropen Fullerpartikel wird um die Anordnung der elektrischen Verbindungsaufbauten abgegeben. Ein Gas wird plotzlich in die Vakuumumgebung gegeben, um eine Implosion der homogenen Mischung zu verursachen. Die Implosion verursacht, dass die homogene Mischung Vertiefungen zwischen dem ersten und zweiten Substrat ohne Agglomerieren der anisotropen Fullerpartikel fullt. Die Mischung, die den Raum zwischen dem ersten und zweiten Substrat fullt, weist e...
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020
In this work, a panel packaging approach based on programmable laser milling, injection molded so... more In this work, a panel packaging approach based on programmable laser milling, injection molded soldering (IMS), and temporary handling technologies has been proposed and demonstrated for micro thin-film-battery (TFB) cells. Micro TFB cells in the dimensions of 2.5mm × 2.5mm × 0.1mm have been successfully packaged and sealed with overmolding solder.
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016
This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip... more This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip cooling. A thermal demonstration vehicle (TDV) has been designed, fabricated and assembled. Radial micro-channels based on deep Si etching was integrated with a manifold chip to form a 2-layer chip stack, which has been assembled using a ceramic substrate and a Cu manifold. A test vehicle with an effective critical heat flux of 340 W/cm2 and uniform cooling has been successfully demonstrated using a dielectric coolant (R1234ze).
International Symposium on Microelectronics, 2010
We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for... more We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting. In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated. In mask-less IMS, the pure molten solder is directly filled i...
International Symposium on Microelectronics, 2014
IMS (injection molded solder) is an advanced solder bumping technology with solder alloy flexibil... more IMS (injection molded solder) is an advanced solder bumping technology with solder alloy flexibility even at very fine pitch and small size. One of key materials for successful fine pitch bumping by IMS is a photoresist material. The photoresist material must be stable at high temperature during the IMS process and be perfectly stripped after the IMS process without any residue on the surface of the substrate. In this study, negative tone liquid photoresist materials were prepared to investigate effects of thermal cure of photoresist on IMS process and stripping performance. With appropriate cure conditions, successful bumping without any film damages at IMS process and any residue at stripping was achieved. Fine pitch bumping down to 40 μm pitch with 20 μm diameter was demonstrated with a Sn-3.0Ag-0.5Cu solder. Also physical and electrical connections for the solder joints of IMS bumps to Ni/Au pads were confirmed using a 80 μm pitch test vehicle.
2006 8th Electronics Packaging Technology Conference, 2006
ABSTRACT The effect of electromigration on the strain and mechanical properties change in SAC sol... more ABSTRACT The effect of electromigration on the strain and mechanical properties change in SAC solder joint is reported. In-situ digital image speckle correlation technology was used to study the strain evolution at the lead-free solder joints during electromigration. The tensile test structure of a solder ball connected by two Cu wires of 300mum diameters was prepared and tested. It is found that, during electromigration, with the atoms moving from the cathode to the anode, a tensile strain was created at the cathode region; while a compressive strain was observed at the anode region. And the strain difference between the cathode and anode kept increasing with the time of electromigration. The mechanical property of Pb-free solder joints with and without electromigration is studied by the nano-indentation continuous stiffness measurement (CSM) technology. At 100 degC, the applied current density was from 0 A/cm2 to 5 times 103 A/cm2 and the time from 3 to 144 hrs. An array of 500 nm indentations was created by the nanoindenter from the cathode area, across the bulk of the solder, to the anode area. The change of Young's modulus and the hardness at the cathode and the anode was calculated from the CSM nano-indentation test. The results show that, the Young's modulus and the hardness of the anode were higher than the original values. It increases with increasing electromigration time or higher current density. On the other hand, the Young's modulus and hardness at the cathode were lower than the original values and they decrease with increasing electromigration time or higher current density. Therefore, there is a change of mechanical properties at the cathode and the anode region of the lead-free SAC solder joints due to electromigration.
2015 Symposium on VLSI Technology (VLSI Technology), 2015
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regul... more This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V 2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast response, steady-state regulation, and fixed switching frequency. Peak efficiency of 82% for conversion from 1.66 V to 0.83 V is observed at a 150 MHz per-phase switching frequency. This is the first demonstration of high-speed voltage regulation using on-chip magnetic-core inductors in a 3D stack and achieves sub-µs dynamic supply voltage scaling for high-density embedded processing applications.
2008 58th Electronic Components and Technology Conference, 2008
Abstract We report here preliminary results on a new Cu-cored flip chip structure combining C4NP ... more Abstract We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which ...
2012 IEEE 62nd Electronic Components and Technology Conference, 2012
ABSTRACT Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip ch... more ABSTRACT Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 × 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13×17mm and the test substrate was 42.5×42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag >; 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag >; 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k
2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The w... more In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.
2009 59th Electronic Components and Technology Conference, 2009
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
We have studied the effect of thickness of Cu under bump metallization (UBM) from 5 mum, 10 mum t... more We have studied the effect of thickness of Cu under bump metallization (UBM) from 5 mum, 10 mum to 50 mum on electromigration induced failure mechanism in flip chip solder joints. In the case of 5 mum Cu UBM, due to the direct current crowding effect at the UBM/solder interface, the failure mode induced by electromigration was the loss of
2013 IEEE 63rd Electronic Components and Technology Conference, 2013
ABSTRACT In this work, differential heating/cooling chip join process was developed for coreless ... more ABSTRACT In this work, differential heating/cooling chip join process was developed for coreless flip chip packaging to minimize warpage change of coreless substrates during the bonding process. A chip was vacuumed to a bonder head and a coreless substrate was vacuumed on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference provides a substantially matched thermal expansion between the silicon chip and the coreless substrate. This minimizes stress induced by low coefficient of thermal expansion (CTE) mismatch during flip chip assembly. Both thermal and mechanical modeling were performed to provide more detailed information about the temperature distributions and warpage levels for all package components during the chip join process. Mechanical modeling of the chip join process confirmed that by implementing differential heating/cooling chip join process the stresses within the solder bumps can be reduced by more than 20% and the stresses in the low-k layers within the chip can be reduced by more than 25%. Our evaluations used semiconductor chips with a known low-k dielectric and SnAg solder bumps. The size of the test chip was approximately 19 mm × 19 mm with less than 150 μm pitch. The coreless substrate was 55 mm × 55 mm with 8+1 layers. The samples were bonded with an optimized differential heating/cooling chip join process. The experimental results showed that there were no C4 (Controlled Collapsible Chip Connection) bumps bridging, non-wets, nor low-k delamination in the large die with coreless package. Reliability data showed no failures in any of the tested modules.
ACS Nano, 2012
We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a thre... more We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a three-dimensional (3D) substrate for hydrogenated amorphous silicon (a-Si:H) solar cells. The method is based on self-assembled tin nanospheres with sizes in the range of 20 nm to 1.2 μm. By depositing these spheres on glass substrates and using them as an etch mask, we demonstrate the formation of glass nanopillars or nanocones, depending on process conditions. After deposition of 150 nm thick a-Si:H solar cell p-i-n stacks on the glass nanocones, we show an output efficiency of 7.6% with a record fill factor of ~69% for a nanopillar-based 3D solar cell. This represents up to 40% enhanced efficiency compared to planar solar cells and, to the best of our knowledge, is the first demonstration of nanostructured p-i-n a-Si:H solar cells on glass that is textured without optical lithography patterning methods.
Integrated Optics: Devices, Materials, and Technologies XXII, 2018
The packaging of photonic devices remains a hindering challenge to the deployment of integrated p... more The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019
Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-t... more Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-throughput assembly of components with sub-micron accuracy. This is especially impactful to integrated photonics as used for high speed optical communication and sensors [1,2]. Assembly yield hinges on the details of solder-induced forces and on the geometry of the melted solder surface. Low curvature of melted solder is best to balance solder forces for optimal re-alignment yield but leads to shallow contact angles and solder de-wetting on traditional solder pads. We introduce and demonstrate the concept of recessed solder pads with shallow angled edges. Such geometry enables arbitrarily-low curvature of the molten solder surface and even flat or slightly concave shapes. The solder stays anchored at the angled edges of recessed pads and can be made to flow in long and narrow conduits. Both aspects are key to widening the fabrication and process window for the solder-induced chip-alignment technology.
Optical Fiber Communication Conference, 2017
IEEE Journal of Selected Topics in Quantum Electronics, 2016
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
We developed a tool of molten solder injection which is able to form solder bumping on wafers, ce... more We developed a tool of molten solder injection which is able to form solder bumping on wafers, ceramic/organic substrates, flexible circuits, and Si via filling from fine pitch to large pitch. One tool has capabilities of solder bumping on wafers from 15 microns diameter to larger than 1000 microns diameter, bumping on organic substrates from flip chip pre-solder to BGA size, soldering on flexible circuits with < 25 microns width of circle and square shape, and via filling of Si wafer with various via diameters. Also, this tool enables the change of solder composition to be very easy and fast because simple switch of the solder injection head allows to change the solder composition like switching an ink cartridge in an inkjet printer. The solder injection tool head contains a reservoir of molten solder of desired composition and a slot through which the molten solder is injected with an optimized combination of pressure and temperature. The solder injection slot of the head is configured in the portion of compliant material and low friction material such that this combination provides good wiping characteristics as well as allowing the IMS head to better track surface topography of an organic substrate. This paper will review key attributes of the molten solder injection tool and discuss differences in the processes required for each different applications of solder bumping on Si wafers and ceramic/organic/flexible substrates as well as filling solder into Si vias. We will describe data of 200mm wafer bumping results with different bump diameters and shape, solder bumping results on organic and ceramic substrates, soldering on flexible circuits, and via filling results of Si. Also, solder alloy flexibility of this technology has been demonstrated from low melting temperature Pb-free solders to high melting temperature Pb-free solders.
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018
This paper proposed a high-speed precision handling technology of micro-chip using programmable l... more This paper proposed a high-speed precision handling technology of micro-chip using programmable laser debonding technology for fan-out wafer level packaging (FOWLP) application, and investigated the programmable capability, the speed and the accuracy with laser debonding experiments on chips down to 25umX25um. The proposed FOWLP approach has features of: (a) all steps are based on wafer-level processes by using programmable laser debonding technology to achieve the reconstituted wafer, enabling high-speed precision hanldinghandling technology for micro-chip. And, (b) two bonding interface layers, one high-strength adhesive layer for chips firmly joined to handler and the other UV-sensitive layer for easily laser debonding, can improve the die-shift issues. The successfully debonding results, including selectively debonding 200umX400um chips from handler wafer and specifically debonding 25umX25um chips forming the letters "IBM", indicates the programmable capability of this...
Verfahren zum Bereitstellen eines Matrixmaterials zwischen einem gebunden Paar von Substraten, wo... more Verfahren zum Bereitstellen eines Matrixmaterials zwischen einem gebunden Paar von Substraten, wobei eine homogene Verteilung von anisotropen Fullermaterialien bereitgestellt ist. Funktionalisierte anisotrope Fullerpartikel sind gleichmasig mit einem Matrixmaterial gemischt, um eine homogene Mischung auszubilden. Ein gebundener Aufbau eines ersten Substrats und eines zweiten Substrats mit einer Anordnung von elektrischen Verbindungsaufbauten ist innerhalb einer Vakuumumgebung platziert. Die homogene Mischung des Matrixmaterials und der anisotropen Fullerpartikel wird um die Anordnung der elektrischen Verbindungsaufbauten abgegeben. Ein Gas wird plotzlich in die Vakuumumgebung gegeben, um eine Implosion der homogenen Mischung zu verursachen. Die Implosion verursacht, dass die homogene Mischung Vertiefungen zwischen dem ersten und zweiten Substrat ohne Agglomerieren der anisotropen Fullerpartikel fullt. Die Mischung, die den Raum zwischen dem ersten und zweiten Substrat fullt, weist e...
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020
In this work, a panel packaging approach based on programmable laser milling, injection molded so... more In this work, a panel packaging approach based on programmable laser milling, injection molded soldering (IMS), and temporary handling technologies has been proposed and demonstrated for micro thin-film-battery (TFB) cells. Micro TFB cells in the dimensions of 2.5mm × 2.5mm × 0.1mm have been successfully packaged and sealed with overmolding solder.
2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016
This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip... more This paper reports on the integration and packaging of embedded radial micro-channels for 3D chip cooling. A thermal demonstration vehicle (TDV) has been designed, fabricated and assembled. Radial micro-channels based on deep Si etching was integrated with a manifold chip to form a 2-layer chip stack, which has been assembled using a ceramic substrate and a Cu manifold. A test vehicle with an effective critical heat flux of 340 W/cm2 and uniform cooling has been successfully demonstrated using a dielectric coolant (R1234ze).
International Symposium on Microelectronics, 2010
We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for... more We report the results of a new pre-solder bumping technology of injection molded solder (IMS) for fine pitch organic substrates. Pure molten solder is injected through a reusable film mask (mask IMS) or directly injected without a mask (mask-less IMS) on the pads of an organic substrate to overcome the limitation of current pre-solder bumping technologies such as solder paste stencil printing and micro-ball mounting. In the case of mask IMS, targeted solder height over the solder resist (SR) is designed into the mask which has desirable thickness and hole sizes. Three different solder bump heights such as 30, 50, and 70 microns over SR were demonstrated for commercial organic substrates which have a pitch of 150 μm for 5,000 area array pads. To show the extendibility of the mask IMS bumping method to very fine pitch applications, 100 μm pitch bumping of 10,000 pads and 80 μm pitch bumping of 15,000 pads were demonstrated. In mask-less IMS, the pure molten solder is directly filled i...
International Symposium on Microelectronics, 2014
IMS (injection molded solder) is an advanced solder bumping technology with solder alloy flexibil... more IMS (injection molded solder) is an advanced solder bumping technology with solder alloy flexibility even at very fine pitch and small size. One of key materials for successful fine pitch bumping by IMS is a photoresist material. The photoresist material must be stable at high temperature during the IMS process and be perfectly stripped after the IMS process without any residue on the surface of the substrate. In this study, negative tone liquid photoresist materials were prepared to investigate effects of thermal cure of photoresist on IMS process and stripping performance. With appropriate cure conditions, successful bumping without any film damages at IMS process and any residue at stripping was achieved. Fine pitch bumping down to 40 μm pitch with 20 μm diameter was demonstrated with a Sn-3.0Ag-0.5Cu solder. Also physical and electrical connections for the solder joints of IMS bumps to Ni/Au pads were confirmed using a 80 μm pitch test vehicle.
2006 8th Electronics Packaging Technology Conference, 2006
ABSTRACT The effect of electromigration on the strain and mechanical properties change in SAC sol... more ABSTRACT The effect of electromigration on the strain and mechanical properties change in SAC solder joint is reported. In-situ digital image speckle correlation technology was used to study the strain evolution at the lead-free solder joints during electromigration. The tensile test structure of a solder ball connected by two Cu wires of 300mum diameters was prepared and tested. It is found that, during electromigration, with the atoms moving from the cathode to the anode, a tensile strain was created at the cathode region; while a compressive strain was observed at the anode region. And the strain difference between the cathode and anode kept increasing with the time of electromigration. The mechanical property of Pb-free solder joints with and without electromigration is studied by the nano-indentation continuous stiffness measurement (CSM) technology. At 100 degC, the applied current density was from 0 A/cm2 to 5 times 103 A/cm2 and the time from 3 to 144 hrs. An array of 500 nm indentations was created by the nanoindenter from the cathode area, across the bulk of the solder, to the anode area. The change of Young's modulus and the hardness at the cathode and the anode was calculated from the CSM nano-indentation test. The results show that, the Young's modulus and the hardness of the anode were higher than the original values. It increases with increasing electromigration time or higher current density. On the other hand, the Young's modulus and hardness at the cathode were lower than the original values and they decrease with increasing electromigration time or higher current density. Therefore, there is a change of mechanical properties at the cathode and the anode region of the lead-free SAC solder joints due to electromigration.
2015 Symposium on VLSI Technology (VLSI Technology), 2015
This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regul... more This paper presents a three-dimensional (3D) fully integrated high-speed multiphase voltage regulator. A complete switched-inductor regulator is integrated with a four-plane NoC in a two-high chip stack combining integrated magnetics, through-silicon vias (TSVs), and 45-nm SOI CMOS devices. Quasi-V 2 hysteretic control is implemented over eight injection-locked fixed-frequency phases to achieve fast response, steady-state regulation, and fixed switching frequency. Peak efficiency of 82% for conversion from 1.66 V to 0.83 V is observed at a 150 MHz per-phase switching frequency. This is the first demonstration of high-speed voltage regulation using on-chip magnetic-core inductors in a 3D stack and achieves sub-µs dynamic supply voltage scaling for high-density embedded processing applications.
2008 58th Electronic Components and Technology Conference, 2008
Abstract We report here preliminary results on a new Cu-cored flip chip structure combining C4NP ... more Abstract We report here preliminary results on a new Cu-cored flip chip structure combining C4NP (Controlled Collapse Chip Connect New Process) with Cu spheres for high density interconnections. C4NP is a new wafer bumping technology developed by IBM in which ...
2012 IEEE 62nd Electronic Components and Technology Conference, 2012
ABSTRACT Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip ch... more ABSTRACT Wafer level underfill (WLUF), coated and B-staged on the wafer before dicing and flip chip bonding, protects and preserves interconnects and Back-End-of-Line (BEOL) structures by the presence of the underfill during the chip joining process. However, there are significant new challenges in formulating WLUF materials and developing the processes for area array flip chip packaging of silicon chips on organic substrates. The use of highly filled WLUF in conjunction with Ultra Low-k (ULK) chips which are larger than 10 × 10 mm and interconnected with Cu pillars to organic substrates has not yet been reported in the literature. It has been very challenging to achieve 100% electrically and metallurgically good Pb-free solder joints without WLUF voids. In this paper, details of flip chip packaging processes with highly filled WLUF materials (60 wt% fillers) will be presented including coating, dicing, bonding, and curing. The size of the test chip was 13×17mm and the test substrate was 42.5×42.5mm with over 8,000 area array interconnects. The chip bumps were 40 micron tall Cu pillars capped with 10 microns of SnAg solder (Ag >; 1.5 wt%) and the pre-solder on the substrate was SnAgCu (Ag >; 3.0 wt%). During the WLUF spin coating process, it is important to maintain uniform filler distribution as well as thickness uniformity. We achieved a tack-free surface after B-stage cure and the surface roughness was less than 0.2 micron. Since the wafer has ULK (k
2014 IEEE 64th Electronic Components and Technology Conference (ECTC), 2014
In this paper, we will describe a new low cost solder bumping technology for use on wafers. The w... more In this paper, we will describe a new low cost solder bumping technology for use on wafers. The wafer IMS (injection molded solder) process can form fine pitch solder bumps on wafers, while offering greater solder alloy flexibility. This method is also applicable to form uniform solder bump heights when a wafer has different size and shape of I/O pads. The wafer IMS bumping process uses a solder injection head that melts the desired bulk solder alloy composition and then dispenses the molten solder into resist material cavities on wafers within a nitrogen environment. The injected molten solder contacts and wets to the metal pads without flux, thus forming intermetallic compounds at the solder/pad interface. After stripping the resist material, solder bumps exhibit straight side walls and round tops as the solders have solidified inside the cavities of this resist film. This particular geometry is unique and offers a ready-for-substrate bonding condition without an additional reflow step. In the case of using Cu pillars, one resist material is used for both Cu electroplating and molten solder injection. After patterning the resist material, the Cu pillars are electroplated to the desired height, and the remaining cavities of resist material are filled by the injection of molten solder. The final bump height is defined by the thickness of the resist material. Therefore, any non-uniformity of Cu pillar height across a wafer is masked by the final solder bump uniformity. A prototype tool for wafer IMS bumping technology has been developed and solder bumping has successfully been demonstrated with Sn-3.0Ag-0.5Cu solder on 200mm wafers. The test wafer employed interconnects pads of four different diameters and three different shapes. Other solder compositions have also been tried successfully.
2009 59th Electronic Components and Technology Conference, 2009
2007 Proceedings 57th Electronic Components and Technology Conference, 2007
We have studied the effect of thickness of Cu under bump metallization (UBM) from 5 mum, 10 mum t... more We have studied the effect of thickness of Cu under bump metallization (UBM) from 5 mum, 10 mum to 50 mum on electromigration induced failure mechanism in flip chip solder joints. In the case of 5 mum Cu UBM, due to the direct current crowding effect at the UBM/solder interface, the failure mode induced by electromigration was the loss of
2013 IEEE 63rd Electronic Components and Technology Conference, 2013
ABSTRACT In this work, differential heating/cooling chip join process was developed for coreless ... more ABSTRACT In this work, differential heating/cooling chip join process was developed for coreless flip chip packaging to minimize warpage change of coreless substrates during the bonding process. A chip was vacuumed to a bonder head and a coreless substrate was vacuumed on a base plate and they were held at different elevated temperatures during the bonding process. The temperature difference provides a substantially matched thermal expansion between the silicon chip and the coreless substrate. This minimizes stress induced by low coefficient of thermal expansion (CTE) mismatch during flip chip assembly. Both thermal and mechanical modeling were performed to provide more detailed information about the temperature distributions and warpage levels for all package components during the chip join process. Mechanical modeling of the chip join process confirmed that by implementing differential heating/cooling chip join process the stresses within the solder bumps can be reduced by more than 20% and the stresses in the low-k layers within the chip can be reduced by more than 25%. Our evaluations used semiconductor chips with a known low-k dielectric and SnAg solder bumps. The size of the test chip was approximately 19 mm × 19 mm with less than 150 μm pitch. The coreless substrate was 55 mm × 55 mm with 8+1 layers. The samples were bonded with an optimized differential heating/cooling chip join process. The experimental results showed that there were no C4 (Controlled Collapsible Chip Connection) bumps bridging, non-wets, nor low-k delamination in the large die with coreless package. Reliability data showed no failures in any of the tested modules.
ACS Nano, 2012
We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a thre... more We introduce a cost-effective method of forming size-tunable arrays of nanocones to act as a three-dimensional (3D) substrate for hydrogenated amorphous silicon (a-Si:H) solar cells. The method is based on self-assembled tin nanospheres with sizes in the range of 20 nm to 1.2 μm. By depositing these spheres on glass substrates and using them as an etch mask, we demonstrate the formation of glass nanopillars or nanocones, depending on process conditions. After deposition of 150 nm thick a-Si:H solar cell p-i-n stacks on the glass nanocones, we show an output efficiency of 7.6% with a record fill factor of ~69% for a nanopillar-based 3D solar cell. This represents up to 40% enhanced efficiency compared to planar solar cells and, to the best of our knowledge, is the first demonstration of nanostructured p-i-n a-Si:H solar cells on glass that is textured without optical lithography patterning methods.
Integrated Optics: Devices, Materials, and Technologies XXII, 2018
The packaging of photonic devices remains a hindering challenge to the deployment of integrated p... more The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.
2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019
Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-t... more Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-throughput assembly of components with sub-micron accuracy. This is especially impactful to integrated photonics as used for high speed optical communication and sensors [1,2]. Assembly yield hinges on the details of solder-induced forces and on the geometry of the melted solder surface. Low curvature of melted solder is best to balance solder forces for optimal re-alignment yield but leads to shallow contact angles and solder de-wetting on traditional solder pads. We introduce and demonstrate the concept of recessed solder pads with shallow angled edges. Such geometry enables arbitrarily-low curvature of the molten solder surface and even flat or slightly concave shapes. The solder stays anchored at the angled edges of recessed pads and can be made to flow in long and narrow conduits. Both aspects are key to widening the fabrication and process window for the solder-induced chip-alignment technology.
Optical Fiber Communication Conference, 2017
IEEE Journal of Selected Topics in Quantum Electronics, 2016