Nhat Nguyen - Academia.edu (original) (raw)

Papers by Nhat Nguyen

Research paper thumbnail of Interface with variable data rate

Research paper thumbnail of A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

Research paper thumbnail of A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

2008 IEEE Symposium on VLSI Circuits, 2008

Research paper thumbnail of An Adaptive Body-Biased Clock Generation System in 28nm CMOS

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

ABSTRACT An adaptive forward body biasing technique is implemented in a clock generation and dist... more ABSTRACT An adaptive forward body biasing technique is implemented in a clock generation and distribution test chip for memory interface applications to enable wide-range and high-fidelity operation. The proposed clock generation system employs a self-body-biased ring voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to adaptively adjust device body voltages over process and temperature variations. Moreover, a differential body-biasing technique incorporated in a duty cycle corrector (DCC) achieves effective correction range with minimal power overhead. The adaptive self-body-biasing technique extends PLL frequency locking range by more than 20 percent while reducing power supply induced jitter (PSIJ) by maximum 25 percent for increased yield and reliable operation.

Research paper thumbnail of A Si bipolar monolithic RF bandpass amplifier

IEEE Journal of Solid-State Circuits, 1992

Research paper thumbnail of A 1.8-GHz monolithic LC voltage-controlled oscillator

IEEE Journal of Solid-State Circuits, 1992

Page 1. 444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 A 1.8-GHz Monolithic... more Page 1. 444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 A 1.8-GHz Monolithic LC Voltage-Controlled Oscillator Nhat M. Nguyen, Student Member, IEEE, and Robert G. Meyer, Fellow, IEEE Abstract ...

Research paper thumbnail of Start-up and frequency stability in high-frequency oscillators

IEEE Journal of Solid-State Circuits, 1992

Research paper thumbnail of Si IC-compatible inductors and LC passive filters

IEEE Journal of Solid-State Circuits, 1990

Page 1. 1028 APPENDIX &-ENHANCEMENT EFFECTS IN BANDPASS STRUCTURE OF FIG. 4 The c... more Page 1. 1028 APPENDIX &-ENHANCEMENT EFFECTS IN BANDPASS STRUCTURE OF FIG. 4 The characteristic equation of the filter of Fig. 4 using ideal OTAs can be expressed by with ideal pole frequency w, = g , / C and pole quality factor Q = gQD/gQ,. ...

Research paper thumbnail of A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

IEEE Journal of Solid-State Circuits, 2000

Research paper thumbnail of PLL lock detection circuit using edge detection

Research paper thumbnail of Design challenges of low-power and high-speed memory interface in advanced CMOS technology

2011 Symposium on Vlsi Technology Digest of Technical Papers, 2011

ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are... more ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile memory interface to meet aggressive performance and power targets with conventional technology.

Research paper thumbnail of PLL lock detection circuit using edge detection and a state machine

Research paper thumbnail of Delay locked loop circuitry for clock delay adjustment

Research paper thumbnail of Clock-data recovery ("CDR") circuit, apparatus and method for variable frequency data

Research paper thumbnail of A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004

CMOS technology with a IV nominal supply. To minimize area and power consumption, the cell uses a... more CMOS technology with a IV nominal supply. To minimize area and power consumption, the cell uses a single dual-loop PLL. Gate-current leakage compensator is used to mitigate gate-current leakage in the PLL loop-filter capacitor. The quad cell consumes 73mWilink at 3.125Gbps ...

Research paper thumbnail of Design challenges of low-power and high-speed memory interface in advanced CMOS technology

ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are... more ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile memory interface to meet aggressive performance and power targets with conventional technology.

Research paper thumbnail of Design challenges for high performance and power efficient graphics and mobile memory interfaces

Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, 2011

Future generation graphics applications require more than 1TB/s memory bandwidth with a constant ... more Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in today's systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.

Research paper thumbnail of Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

Page 1. Design and Characterization of a 12.8GB/s Low Power Differential Memory System for Mobile... more Page 1. Design and Characterization of a 12.8GB/s Low Power Differential Memory System for Mobile Applications Dan Oh, Sam Chang, Chris Madden, Joong-Ho Kim, Ralf Schmitt, Ming Li,Chuck Yuan Fred Ware, Brian Leibowitz, Yohan Frans, and Nhat Nguyen Rambus Inc. ...

Research paper thumbnail of Power-efficient I/O design considerations for high-bandwidth applications

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011

Abstract Power-efficiency results from several generations of I/O interfaces with specific goals ... more Abstract Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system, the ...

Research paper thumbnail of Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, 2010

Abstract—This paper experimentally investigates substrate noise and its impact on the jitter perf... more Abstract—This paper experimentally investigates substrate noise and its impact on the jitter performance of a low-power memory controller PHY interface using an on-chip substrate noise measurement structure. A previously proven on-chip supply noise measurement method is extended ...

Research paper thumbnail of Interface with variable data rate

Research paper thumbnail of A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007

Research paper thumbnail of A 16-Gb/s differential I/O cell with 380fs RJ in an emulated 40nm DRAM process

2008 IEEE Symposium on VLSI Circuits, 2008

Research paper thumbnail of An Adaptive Body-Biased Clock Generation System in 28nm CMOS

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

ABSTRACT An adaptive forward body biasing technique is implemented in a clock generation and dist... more ABSTRACT An adaptive forward body biasing technique is implemented in a clock generation and distribution test chip for memory interface applications to enable wide-range and high-fidelity operation. The proposed clock generation system employs a self-body-biased ring voltage-controlled oscillator (VCO) in a phase-locked loop (PLL) to adaptively adjust device body voltages over process and temperature variations. Moreover, a differential body-biasing technique incorporated in a duty cycle corrector (DCC) achieves effective correction range with minimal power overhead. The adaptive self-body-biasing technique extends PLL frequency locking range by more than 20 percent while reducing power supply induced jitter (PSIJ) by maximum 25 percent for increased yield and reliable operation.

Research paper thumbnail of A Si bipolar monolithic RF bandpass amplifier

IEEE Journal of Solid-State Circuits, 1992

Research paper thumbnail of A 1.8-GHz monolithic LC voltage-controlled oscillator

IEEE Journal of Solid-State Circuits, 1992

Page 1. 444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 A 1.8-GHz Monolithic... more Page 1. 444 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 27. NO. 3. MARCH 1992 A 1.8-GHz Monolithic LC Voltage-Controlled Oscillator Nhat M. Nguyen, Student Member, IEEE, and Robert G. Meyer, Fellow, IEEE Abstract ...

Research paper thumbnail of Start-up and frequency stability in high-frequency oscillators

IEEE Journal of Solid-State Circuits, 1992

Research paper thumbnail of Si IC-compatible inductors and LC passive filters

IEEE Journal of Solid-State Circuits, 1990

Page 1. 1028 APPENDIX &-ENHANCEMENT EFFECTS IN BANDPASS STRUCTURE OF FIG. 4 The c... more Page 1. 1028 APPENDIX &-ENHANCEMENT EFFECTS IN BANDPASS STRUCTURE OF FIG. 4 The characteristic equation of the filter of Fig. 4 using ideal OTAs can be expressed by with ideal pole frequency w, = g , / C and pole quality factor Q = gQD/gQ,. ...

Research paper thumbnail of A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

IEEE Journal of Solid-State Circuits, 2000

Research paper thumbnail of PLL lock detection circuit using edge detection

Research paper thumbnail of Design challenges of low-power and high-speed memory interface in advanced CMOS technology

2011 Symposium on Vlsi Technology Digest of Technical Papers, 2011

ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are... more ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile memory interface to meet aggressive performance and power targets with conventional technology.

Research paper thumbnail of PLL lock detection circuit using edge detection and a state machine

Research paper thumbnail of Delay locked loop circuitry for clock delay adjustment

Research paper thumbnail of Clock-data recovery ("CDR") circuit, apparatus and method for variable frequency data

Research paper thumbnail of A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004

CMOS technology with a IV nominal supply. To minimize area and power consumption, the cell uses a... more CMOS technology with a IV nominal supply. To minimize area and power consumption, the cell uses a single dual-loop PLL. Gate-current leakage compensator is used to mitigate gate-current leakage in the PLL loop-filter capacitor. The quad cell consumes 73mWilink at 3.125Gbps ...

Research paper thumbnail of Design challenges of low-power and high-speed memory interface in advanced CMOS technology

ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are... more ABSTRACT Design requirements for low-power and high-speed memory interfaces in mobile systems are discussed within the context of CMOS process scaling. Key challenges include process variations, low Vdd/Vth ratio, interconnect parasitics, and model accuracy of key process parameters. It is shown that careful system architecture along with appropriate circuit techniques allow mobile memory interface to meet aggressive performance and power targets with conventional technology.

Research paper thumbnail of Design challenges for high performance and power efficient graphics and mobile memory interfaces

Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, 2011

Future generation graphics applications require more than 1TB/s memory bandwidth with a constant ... more Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in today's systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.

Research paper thumbnail of Design and characterization of a 12.8GB/s low power differential memory system for mobile applications

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

Page 1. Design and Characterization of a 12.8GB/s Low Power Differential Memory System for Mobile... more Page 1. Design and Characterization of a 12.8GB/s Low Power Differential Memory System for Mobile Applications Dan Oh, Sam Chang, Chris Madden, Joong-Ho Kim, Ralf Schmitt, Ming Li,Chuck Yuan Fred Ware, Brian Leibowitz, Yohan Frans, and Nhat Nguyen Rambus Inc. ...

Research paper thumbnail of Power-efficient I/O design considerations for high-bandwidth applications

2011 IEEE Custom Integrated Circuits Conference (CICC), 2011

Abstract Power-efficiency results from several generations of I/O interfaces with specific goals ... more Abstract Power-efficiency results from several generations of I/O interfaces with specific goals are presented as well as the tradeoffs made within and across those designs. Foundational work in active-power reduction at a single rate for a symmetric system, the ...

Research paper thumbnail of Investigating substrate coupling noise impact on low-power memory controller PHY interface using on-chip measurement structure

19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, 2010

Abstract—This paper experimentally investigates substrate noise and its impact on the jitter perf... more Abstract—This paper experimentally investigates substrate noise and its impact on the jitter performance of a low-power memory controller PHY interface using an on-chip substrate noise measurement structure. A previously proven on-chip supply noise measurement method is extended ...