P. Marwedel - Academia.edu (original) (raw)

Papers by P. Marwedel

Research paper thumbnail of Register File Synthesis in ASIP Design

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Research paper thumbnail of Cache-aware scratchpad allocation algorithm

Proceedings Design, Automation and Test in Europe Conference and Exhibition

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Research paper thumbnail of Methods for retargetable DSP code generation

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing

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Research paper thumbnail of Analysis of the In uence of Register File Size

Interest in low power embedded systems has increased considerably in the past few years. To produ... more Interest in low power embedded systems has increased considerably in the past few years. To produce low power code and to allow an estimation of power consumption of software running on embedded systems, a power model was developed based on physical measurement using an evaluation board and integrated into a compiler and pro ler. The compiler uses the power information to choose instruction sequences consuming less power, whereas the pro ler gives information about the total power consumed during execution of the generated program.

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Research paper thumbnail of Topic Chairs

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Research paper thumbnail of Using an Energy Aware Compiler Framework to Evaluate Changes in Register File Size towards ASIP-Design£

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Research paper thumbnail of Three decades of hardware description languages in Europe

This paper binds together a collection of short presentations on Hardware Description Languages(H... more This paper binds together a collection of short presentations on Hardware Description Languages(HDLs) developed in Europe and provides a view of the history of HDLs during the last three decades. This historical review wants to present the ideas, conceived in these previous languages, which are now implemented in the standard languages. Furthermore, this paper will highlight those early concepts which yet need to be implemented in the evolving standards or could provide a way to unify them (like VHDL or Verilog or SDL) within a formally defined multi-language environment. Among a large number of European works over 3 decades, we have selected a sample from different countries France, Germany, U.K, Italy, which have been implemented and used reliably in various segments of the industry. The selected HDLs, with the date of origination, are: CASSANDRE (1967), MIMOLA (1977), DACAPO (1977), ELLA(1979), ART (1980), and CASCADE (1981). We do not pretend to any exhaustive review, which is not the goal of this presentation, and have consciously left aside several works as valuable as those selected. We have not addressed for example ≪ synchronous languages ≫ very well developed in France, such as ESTEREL, LUSTRE or SIGNAL. Several other works existed in Germany, such as KARL, which was popular in the eighties, and benefits from a large bibliography or REGLAN. We should mention also among those HDLs not presented here CONLAN (a major international standardization effort involving a notable European contribution). We have tried to compare the main features of the chosen languages according to a list of criteria and briefly identify those which are still missing in the recognized worldwide standards.

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Research paper thumbnail of Reducing energy consumption by dynamic copying of instructions onto onchip memory

15th International Symposium on System Synthesis, 2002.

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Research paper thumbnail of System Software

Springer Netherlands eBooks, 2011

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Research paper thumbnail of Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006

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Research paper thumbnail of An automatic framework for dynamic data structures optimization in C

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010

Modern embedded devices require highly optimized code in order to efficiently run the wide range ... more Modern embedded devices require highly optimized code in order to efficiently run the wide range of applications they are designed for. However, most modern applications are getting more and more dynamic, which at the software level, translates in the use of dynamic data structures like dynamic arrays and lists. State of the art solutions for the optimization of these dynamic

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Research paper thumbnail of Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software

Design, Automation and Test in Europe

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Research paper thumbnail of Optimized address assignment for DSPs with SIMD memory accesses

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001

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Research paper thumbnail of Data partitioning for maximal scratchpad usage

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

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Research paper thumbnail of Analysis of the influence of register file size on energy consumption, code size, and execution time

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001

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Research paper thumbnail of Software synthesis and code generation for signal processing systems

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000

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Research paper thumbnail of Soft Error Handling for Embedded Systems using Compiler-OS Interaction

Dependable Embedded Systems

Advancing semiconductor technologies increasingly fail to provide expected gains in cost and ener... more Advancing semiconductor technologies increasingly fail to provide expected gains in cost and energy reductions due to reaching the physical limits of Moore’s Law and Dennard scaling. Instead, shrinking semiconductor feature sizes increase a circuit’s susceptibility to soft errors. In order to ensure reliable operation, a significant hardware overhead would be required.The FEHLER project (Flexible Error Handling for Embedded Real-Time Systems) introduces error semantics into the software development process which provide a system with information about the criticality of a given data object to soft errors. Using this information, the overhead required for error correction can be reduced significantly for many applications, since only errors affecting critical data have to be corrected.In this chapter, the fundamental components of FEHLER that cooperate at design and runtime of an embedded system are presented. These include static compiler analyses and transformations as well as a fa...

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Research paper thumbnail of STAR-DUST : Hierarchical Test of Embedded Processors by Self-Test Programs

This paper describes the hierarchical test-generation method STAR-DUST, using selftest program ge... more This paper describes the hierarchical test-generation method STAR-DUST, using selftest program generator RESTART, test pattern generator DUST, fault simulator FAUST and SYNOPSYS logic synthesis tools. RESTART aims at supporting self-test of embedded processors. Its integration into the STAR-DUST environment allows test program generation for realistic fault assumptions and provides, for the rst time, experimental data on the fault coverage that can be obtained for full processor models. Experimental data shows that fault masking is not a problem even though the considered processor has to perform result comparison and arithmetic operations in the same ALU.

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Research paper thumbnail of Controlling the influence of PCI DMA transfers on WCET of real-time software

We propose coordinated use of compiler techniques to improvepredictability of timing behavior of ... more We propose coordinated use of compiler techniques to improvepredictability of timing behavior of hard real-time systems, and thus, to tighten their worst-case execution times. We aim at a generic methodology of compiler optimizations that replace the use of unpredictable hardware and operating system features by the use of more predictable features. We call the approach compiler controlled operation, because it is basedon using compilers to control operations that are traditionally controlled by hardware or operating systems. As an example of the approach, we overview our work in progress on a small experimental system.

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Research paper thumbnail of Mmapcopy

Proceedings of the 31st Annual ACM Symposium on Applied Computing - SAC '16, 2016

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Research paper thumbnail of Register File Synthesis in ASIP Design

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Cache-aware scratchpad allocation algorithm

Proceedings Design, Automation and Test in Europe Conference and Exhibition

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Methods for retargetable DSP code generation

Proceedings of 1994 IEEE Workshop on VLSI Signal Processing

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analysis of the In uence of Register File Size

Interest in low power embedded systems has increased considerably in the past few years. To produ... more Interest in low power embedded systems has increased considerably in the past few years. To produce low power code and to allow an estimation of power consumption of software running on embedded systems, a power model was developed based on physical measurement using an evaluation board and integrated into a compiler and pro ler. The compiler uses the power information to choose instruction sequences consuming less power, whereas the pro ler gives information about the total power consumed during execution of the generated program.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Topic Chairs

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Using an Energy Aware Compiler Framework to Evaluate Changes in Register File Size towards ASIP-Design£

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Three decades of hardware description languages in Europe

This paper binds together a collection of short presentations on Hardware Description Languages(H... more This paper binds together a collection of short presentations on Hardware Description Languages(HDLs) developed in Europe and provides a view of the history of HDLs during the last three decades. This historical review wants to present the ideas, conceived in these previous languages, which are now implemented in the standard languages. Furthermore, this paper will highlight those early concepts which yet need to be implemented in the evolving standards or could provide a way to unify them (like VHDL or Verilog or SDL) within a formally defined multi-language environment. Among a large number of European works over 3 decades, we have selected a sample from different countries France, Germany, U.K, Italy, which have been implemented and used reliably in various segments of the industry. The selected HDLs, with the date of origination, are: CASSANDRE (1967), MIMOLA (1977), DACAPO (1977), ELLA(1979), ART (1980), and CASCADE (1981). We do not pretend to any exhaustive review, which is not the goal of this presentation, and have consciously left aside several works as valuable as those selected. We have not addressed for example ≪ synchronous languages ≫ very well developed in France, such as ESTEREL, LUSTRE or SIGNAL. Several other works existed in Germany, such as KARL, which was popular in the eighties, and benefits from a large bibliography or REGLAN. We should mention also among those HDLs not presented here CONLAN (a major international standardization effort involving a notable European contribution). We have tried to compare the main features of the chosen languages according to a list of criteria and briefly identify those which are still missing in the recognized worldwide standards.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Reducing energy consumption by dynamic copying of instructions onto onchip memory

15th International Symposium on System Synthesis, 2002.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of System Software

Springer Netherlands eBooks, 2011

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006

Bookmarks Related papers MentionsView impact

Research paper thumbnail of An automatic framework for dynamic data structures optimization in C

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2010

Modern embedded devices require highly optimized code in order to efficiently run the wide range ... more Modern embedded devices require highly optimized code in order to efficiently run the wide range of applications they are designed for. However, most modern applications are getting more and more dynamic, which at the software level, translates in the use of dynamic data structures like dynamic arrays and lists. State of the art solutions for the optimization of these dynamic

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software

Design, Automation and Test in Europe

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Optimized address assignment for DSPs with SIMD memory accesses

Proceedings of the 2001 conference on Asia South Pacific design automation - ASP-DAC '01, 2001

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Data partitioning for maximal scratchpad usage

Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Analysis of the influence of register file size on energy consumption, code size, and execution time

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Software synthesis and code generation for signal processing systems

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Soft Error Handling for Embedded Systems using Compiler-OS Interaction

Dependable Embedded Systems

Advancing semiconductor technologies increasingly fail to provide expected gains in cost and ener... more Advancing semiconductor technologies increasingly fail to provide expected gains in cost and energy reductions due to reaching the physical limits of Moore’s Law and Dennard scaling. Instead, shrinking semiconductor feature sizes increase a circuit’s susceptibility to soft errors. In order to ensure reliable operation, a significant hardware overhead would be required.The FEHLER project (Flexible Error Handling for Embedded Real-Time Systems) introduces error semantics into the software development process which provide a system with information about the criticality of a given data object to soft errors. Using this information, the overhead required for error correction can be reduced significantly for many applications, since only errors affecting critical data have to be corrected.In this chapter, the fundamental components of FEHLER that cooperate at design and runtime of an embedded system are presented. These include static compiler analyses and transformations as well as a fa...

Bookmarks Related papers MentionsView impact

Research paper thumbnail of STAR-DUST : Hierarchical Test of Embedded Processors by Self-Test Programs

This paper describes the hierarchical test-generation method STAR-DUST, using selftest program ge... more This paper describes the hierarchical test-generation method STAR-DUST, using selftest program generator RESTART, test pattern generator DUST, fault simulator FAUST and SYNOPSYS logic synthesis tools. RESTART aims at supporting self-test of embedded processors. Its integration into the STAR-DUST environment allows test program generation for realistic fault assumptions and provides, for the rst time, experimental data on the fault coverage that can be obtained for full processor models. Experimental data shows that fault masking is not a problem even though the considered processor has to perform result comparison and arithmetic operations in the same ALU.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Controlling the influence of PCI DMA transfers on WCET of real-time software

We propose coordinated use of compiler techniques to improvepredictability of timing behavior of ... more We propose coordinated use of compiler techniques to improvepredictability of timing behavior of hard real-time systems, and thus, to tighten their worst-case execution times. We aim at a generic methodology of compiler optimizations that replace the use of unpredictable hardware and operating system features by the use of more predictable features. We call the approach compiler controlled operation, because it is basedon using compilers to control operations that are traditionally controlled by hardware or operating systems. As an example of the approach, we overview our work in progress on a small experimental system.

Bookmarks Related papers MentionsView impact

Research paper thumbnail of Mmapcopy

Proceedings of the 31st Annual ACM Symposium on Applied Computing - SAC '16, 2016

Bookmarks Related papers MentionsView impact