Puspak Pain - Academia.edu (original) (raw)

Papers by Puspak Pain

Research paper thumbnail of Highly Precise Wire Feeder & Cutter Machine with Stepper Motor Using Atmega32 Microcontroller

Journal of emerging technologies and innovative research, Jun 1, 2021

Microcontroller This article aims to improve the wire feeding technique and as well ATmega32 as t... more Microcontroller This article aims to improve the wire feeding technique and as well ATmega32 as the cutting process of wires. Generally, in industries the Stepper Motor machines which they use is of low quality and less accuracy due to Servo Motor which industries are facing uncalculated losses either due to extra Stepper Driver wire feeding, which causes wastage of material and on the other hand if less amount of material is feed then that piece is rejected and in this way industries are unknowingly facing huge losses at every piece of wire. So as to solve this problem, this proposed design focuses on to use less expensive sensors and implementing the advanced algorithm to achieve the precision and accuracy which helps the industries to attain that amount of production. In this design stepper motor is used for feeding the wire along with three less expensive sensors are used to give feedback to the controller while feeding the wire. During which the controller gives this data from the sensors to the PID control program which manipulates and control the entire precision feeding of wire. Cutting mechanism uses servo motor for cutting the wire.

Research paper thumbnail of Detection of word boundary in Bengali colloquial speech based on pitch profile and Convolutional Neural Network

Turkish Online Journal of Qualitative Inquiry, Jun 30, 2021

Research paper thumbnail of Multi-objective Cuckoo Search in Image Visi-bility Improvement

Turkish Online Journal of Qualitative Inquiry, Jun 30, 2021

Research paper thumbnail of Effects of Different Parameters on Low Frequency Flicker Noise Characterization of GaAs-MESFET

Abstract—Excellent microwave performance and potential for low 1/f noise characteristics, GaAs hi... more Abstract—Excellent microwave performance and potential for low 1/f noise characteristics, GaAs high-power MESFETs have been emerging as most important devices for communication. As Semi-insulating GaAs substrate reduces the effect of parasitic capacitance which in turn improves the speed of device over Si. In this theoretical analysis a simplified cross-sectional structure with Gate length (LG) 0.10 µm & Gate width (W) 0.50 µm is considered to find the power spectral density of the drain current fluctuations in GaAs-MESFET. This chapter presents how Flicker noise is characterized and what is its trend when working at high frequencies and high speed technology. The theoretical analysis on Low Frequency Flicker Noise Characterization of GaAs-MESFETs has been carried out for various gate biases (Vgs) and drain-to source voltage (Vds) to illustrate their anticipated noise performances for high frequency applications by optimizing the parameters ranges.

Research paper thumbnail of IOT Based Smart Monitoring and Irrigation System

This paper proposes an automatic plant irrigation system by using INTERNET OF THINGS (IoT).The sm... more This paper proposes an automatic plant irrigation system by using INTERNET OF THINGS (IoT).The smart object inserted with sensors enables interaction with the physical and logical worlds according to the concept of Internet of Things (IoT). The system is embedded with a moisture sensor that checks the moisture level in the soil. After analysing the values, it provides an adequate amount of water to the crop. The pump automatically switches on and supplies water when the soil is dry. Similarly, when the soil is wet, the pump turns off, and no water is given to the crop. This irrigation system prevents excess water from flowing into the soil, thus reduces wastage of water, electricity and damage to the soil. The purpose is to focus on parameters such as temperature and soil moisture. This is a mobile integrated smart irrigation system using IOT based on application controlled monitoring system. The chief aim behind the design of this project is to control the water supply and monitor ...

Research paper thumbnail of Ai And Iot Based Smart Irrigation System

Turkish Online Journal of Qualitative Inquiry, 2021

In this paper we propose a smart irrigation system which is an advanced solution for weather moni... more In this paper we propose a smart irrigation system which is an advanced solution for weather monitoring that uses artificial intelligence and IoT. This system makes the irrigation system smart. With the increasing depletion of the underground water a smart irrigation system that will help farmer to irrigate his farm is designed. In this system depending on the weather conditions and the soil moisture content the smart system with the helpof AI tries to decision whether the irrigation system will be switched on or not. The AI system will decide based on the input from sensors like temperature, humidity, moisture content of soil, light intensity which are connected over IoT. So this system makes decision making of the farmer easy. Each of the system is trained as per the requirement of the field over which the system is implemented, like tea garden, or paddy field or any organised farm. ..

Research paper thumbnail of Design and Comparative Analysis of Low-Power, High-Speed, 3-Bit Flash ADC for Biomedical Signal Processing Using 45-nm CMOS Technology

Computational Advancement in Communication Circuits and Systems, 2019

The analog-to-digital converter is the key component for communication and signal processing. Thi... more The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.

Research paper thumbnail of Physical Proof and Simulation of Ternary Logic Gate in Ternary Quantum Dot Cellular Automata

Computational Advancement in Communication Circuits and Systems, 2019

Ternary quantum dot cellular automata (tQCA) is an emerging as well as an interesting field of re... more Ternary quantum dot cellular automata (tQCA) is an emerging as well as an interesting field of research area after successful fabrication of binary QCA. Ternary logic is a critical choice for solving greater data storage, faster arithmetic operation on complex data, and so on. In this paper, tQCA basic logic gates like ternary AND, OR, NOT gates and buffers have been reported. tQCA layout for basic logic gates is simulated with tQCA simulation software (TQCA_1.7.0.2). Involvement of coulombic interactive force is also explored as physical proof of NOT gate operation in eight-dot tQCA device model.

Research paper thumbnail of Quantum Random Number Generators for Cryptography: Design and Evaluation

Lecture Notes in Electrical Engineering, 2021

Research paper thumbnail of Power analysis attack resistable hardware cryptographical circuit design using reversible logic gate in quantum cellular automata

Microsystem Technologies, 2019

Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power ... more Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

Research paper thumbnail of Design and Comparative Analysis of Low-Power, High-Speed, 3-Bit Flash ADC for Biomedical Signal Processing Using 45-nm CMOS Technology

Computational Advancement in Communication Circuits and Systems, 2019

The analog-to-digital converter is the key component for communication and signal processing. Thi... more The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.

Research paper thumbnail of Novel True Random Number Generator Based Hardware Cryptographic Architecture Using Quantum-Dot Cellular Automata

International Journal of Theoretical Physics, 2019

Information processing and conventional computing are usually resource constrained; evermore they... more Information processing and conventional computing are usually resource constrained; evermore they need to operate in a physically suspicious environment. Consequently, communication architectures, protocol and its security aspects have been the focus of many recent research works. Our proposal demonstrates how to amend this vulnerable circumstance through a three-stage security scheme in quantum-dot cellular automata (QCA) based nanoarchitecture. The primary objective of this hardware-based cryptographic architecture using QCA is to intend a distinctly secure communication architecture comprising less number of QCA cells, which enchant the comparative performance investigation along with the powerarea constraints. In our proposed design the random bits are extorted from an asymmetrically arranged crossed loop TRNG where the seed circuits are used to boost the volatility of initiated number sequences as well as the distinction of the random numbers. In this work, a novel encryption-decryption prototype for a secure communication system has been implemented. The simulation results are obtained from QCADesigner tool v2.0.3, which fruitfully agreed with the industry standard. An intact evaluation of the proposed TRNG and the comparative analysis with a recent work of TRNG has been authorized by the 7.79% improvements in average energy dissipation for different Kink energy ratio. Altogether the proposed architecture and its contemporary implementation in QCA framework can be recognized by means of the advantages in 7.02% circuit complexity, 11.53% area, and 13.77% average leakage power dissipation with respect to the recent work of TRNG. Thus our proposed novel TRNG based hardware cryptographic architecture can be considered as a potential next-generation networkon-chip (NoC) realization for a large-scale cryptosystem in QCA technology.

Research paper thumbnail of Design of Two Stage Ultra Low Power CMOS Operational Transconductance Amplifier(OTA) Using 180 nm Technology

International journal of advanced research in electrical, electronics and instrumentation engineering, 2016

This paper deals with well-defined design criteria for ultra low power two stage CMOS operational... more This paper deals with well-defined design criteria for ultra low power two stage CMOS operational transconductance amplifiers (OTAs) with simple yet robust implementation in nm dimension. A simple design approach which allows electrical parameters to be univocally related to each circuit element and biasing values for low frequency applications is presented.The operational transconductance amplifier with ±1.8v power supply has been simulated using TANNER Tools ver.13 with 0.18μm CMOS technology which provide expected characteristics with convenient performance for given specification.

Research paper thumbnail of Quantum Random Number Generators for Cryptography: Design and Evaluation

Lecture Notes in Electrical Engineering

Research paper thumbnail of Impacts of COVID-19: A Comprehensive Study Using Linear Regression Analysis in a Predictive Approach

Lecture Notes in Electrical Engineering

Research paper thumbnail of Novel True Random Number Generator Based Hardware Cryptographic Architecture Using Quantum-Dot Cellular Automata

International Journal of Theoretical Physics

Information processing and conventional computing are usually resource constrained; evermore they... more Information processing and conventional computing are usually resource constrained; evermore they need to operate in a physically suspicious environment. Consequently, communication architectures, protocol and its security aspects have been the focus of many recent research works. Our proposal demonstrates how to amend this vulnerable circumstance through a three-stage security scheme in quantum-dot cellular automata (QCA) based nano-architecture. The primary objective of this hardware-based cryptographic architecture using QCA is to intend a distinctly secure communication architecture comprising less number of QCA cells, which enchant the comparative performance investigation along with the power-area constraints. In our proposed design the random bits are extorted from an asymmetrically arranged crossed loop TRNG where the seed circuits are used to boost the volatility of initiated number sequences as well as the distinction of the random numbers. In this work, a novel encryption-decryption prototype for a secure communication system has been implemented. The simulation results are obtained from QCADesigner tool v2.0.3, which fruitfully agreed with the industry standard. An intact evaluation of the proposed TRNG and the comparative analysis with a recent work of TRNG has been authorized by the 7.79% improvements in average energy dissipation for different Kink energy ratio. Altogether the proposed architecture and its contemporary implementation in QCA framework can be recognized by means of the advantages in 7.02% circuit complexity, 11.53% area, and 13.77% average leakage power dissipation with respect to the recent work of TRNG. Thus our proposed novel TRNG based hardware cryptographic architecture can be considered as a potential next-generation network-on-chip (NoC) realization for a large-scale cryptosystem in QCA technology.

Research paper thumbnail of Power analysis attack resistable hardware cryptographical circuit design using reversible logic gate in quantum cellular automata

Microsystem Technologies

Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power ... more Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

Research paper thumbnail of Electrical Characteristics of MESFET Using GaAs, InP and GaN as Substrates

Lecture Notes in Electrical Engineering, 2015

Research paper thumbnail of VLSI Adder Implementation Using Generalized Ling Algorithm

Several addition algorithms are developed to improve speed of addition by manipulating the equati... more Several addition algorithms are developed to improve speed of addition by manipulating the equations used for sum and carry. As with increase in speed of carry and sum computation, the time required for all mathematical calculation in a digital system can be reduced. Carry Look Ahead Adder calculates carry signals in advance based on input signal but carry calculation becomes complex beyond 4 bits. CLA is implemented in three stages; pre-processing, carry generation and parallel addition. Ling Adder is a special kind of CLA Adders. The improvement is in the carry generation stage which is the most intensive one. i.e. pseudo carry h i = c i + c i-1 is propagated instead of c i . Hardware implemented using Ling's algorithm is speedier than Carry Look Ahead adder. These expressions were modified by Ling, reducing complexity of carry generation but at the cost of sum generation complexity. However the total time for addition process is quite less than normal CLA. Ling's algorithm is hardware specific i.e. hardware derived for n bits is specific for it. The implementation differs for every n bit adder. Here hardware specific Ling Adder is transformed to general purpose Ling adder. Proposed adder is based on generalized Ling's algorithm where delay will be same for all addition process. In this thesis, 4,8,16,32 and 64 bit adders for CLA and Ling algorithm is implemented and the time delay, throughput and utilization was compared between two adders.

Research paper thumbnail of Highly Precise Wire Feeder & Cutter Machine with Stepper Motor Using Atmega32 Microcontroller

Journal of emerging technologies and innovative research, Jun 1, 2021

Microcontroller This article aims to improve the wire feeding technique and as well ATmega32 as t... more Microcontroller This article aims to improve the wire feeding technique and as well ATmega32 as the cutting process of wires. Generally, in industries the Stepper Motor machines which they use is of low quality and less accuracy due to Servo Motor which industries are facing uncalculated losses either due to extra Stepper Driver wire feeding, which causes wastage of material and on the other hand if less amount of material is feed then that piece is rejected and in this way industries are unknowingly facing huge losses at every piece of wire. So as to solve this problem, this proposed design focuses on to use less expensive sensors and implementing the advanced algorithm to achieve the precision and accuracy which helps the industries to attain that amount of production. In this design stepper motor is used for feeding the wire along with three less expensive sensors are used to give feedback to the controller while feeding the wire. During which the controller gives this data from the sensors to the PID control program which manipulates and control the entire precision feeding of wire. Cutting mechanism uses servo motor for cutting the wire.

Research paper thumbnail of Detection of word boundary in Bengali colloquial speech based on pitch profile and Convolutional Neural Network

Turkish Online Journal of Qualitative Inquiry, Jun 30, 2021

Research paper thumbnail of Multi-objective Cuckoo Search in Image Visi-bility Improvement

Turkish Online Journal of Qualitative Inquiry, Jun 30, 2021

Research paper thumbnail of Effects of Different Parameters on Low Frequency Flicker Noise Characterization of GaAs-MESFET

Abstract—Excellent microwave performance and potential for low 1/f noise characteristics, GaAs hi... more Abstract—Excellent microwave performance and potential for low 1/f noise characteristics, GaAs high-power MESFETs have been emerging as most important devices for communication. As Semi-insulating GaAs substrate reduces the effect of parasitic capacitance which in turn improves the speed of device over Si. In this theoretical analysis a simplified cross-sectional structure with Gate length (LG) 0.10 µm & Gate width (W) 0.50 µm is considered to find the power spectral density of the drain current fluctuations in GaAs-MESFET. This chapter presents how Flicker noise is characterized and what is its trend when working at high frequencies and high speed technology. The theoretical analysis on Low Frequency Flicker Noise Characterization of GaAs-MESFETs has been carried out for various gate biases (Vgs) and drain-to source voltage (Vds) to illustrate their anticipated noise performances for high frequency applications by optimizing the parameters ranges.

Research paper thumbnail of IOT Based Smart Monitoring and Irrigation System

This paper proposes an automatic plant irrigation system by using INTERNET OF THINGS (IoT).The sm... more This paper proposes an automatic plant irrigation system by using INTERNET OF THINGS (IoT).The smart object inserted with sensors enables interaction with the physical and logical worlds according to the concept of Internet of Things (IoT). The system is embedded with a moisture sensor that checks the moisture level in the soil. After analysing the values, it provides an adequate amount of water to the crop. The pump automatically switches on and supplies water when the soil is dry. Similarly, when the soil is wet, the pump turns off, and no water is given to the crop. This irrigation system prevents excess water from flowing into the soil, thus reduces wastage of water, electricity and damage to the soil. The purpose is to focus on parameters such as temperature and soil moisture. This is a mobile integrated smart irrigation system using IOT based on application controlled monitoring system. The chief aim behind the design of this project is to control the water supply and monitor ...

Research paper thumbnail of Ai And Iot Based Smart Irrigation System

Turkish Online Journal of Qualitative Inquiry, 2021

In this paper we propose a smart irrigation system which is an advanced solution for weather moni... more In this paper we propose a smart irrigation system which is an advanced solution for weather monitoring that uses artificial intelligence and IoT. This system makes the irrigation system smart. With the increasing depletion of the underground water a smart irrigation system that will help farmer to irrigate his farm is designed. In this system depending on the weather conditions and the soil moisture content the smart system with the helpof AI tries to decision whether the irrigation system will be switched on or not. The AI system will decide based on the input from sensors like temperature, humidity, moisture content of soil, light intensity which are connected over IoT. So this system makes decision making of the farmer easy. Each of the system is trained as per the requirement of the field over which the system is implemented, like tea garden, or paddy field or any organised farm. ..

Research paper thumbnail of Design and Comparative Analysis of Low-Power, High-Speed, 3-Bit Flash ADC for Biomedical Signal Processing Using 45-nm CMOS Technology

Computational Advancement in Communication Circuits and Systems, 2019

The analog-to-digital converter is the key component for communication and signal processing. Thi... more The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.

Research paper thumbnail of Physical Proof and Simulation of Ternary Logic Gate in Ternary Quantum Dot Cellular Automata

Computational Advancement in Communication Circuits and Systems, 2019

Ternary quantum dot cellular automata (tQCA) is an emerging as well as an interesting field of re... more Ternary quantum dot cellular automata (tQCA) is an emerging as well as an interesting field of research area after successful fabrication of binary QCA. Ternary logic is a critical choice for solving greater data storage, faster arithmetic operation on complex data, and so on. In this paper, tQCA basic logic gates like ternary AND, OR, NOT gates and buffers have been reported. tQCA layout for basic logic gates is simulated with tQCA simulation software (TQCA_1.7.0.2). Involvement of coulombic interactive force is also explored as physical proof of NOT gate operation in eight-dot tQCA device model.

Research paper thumbnail of Quantum Random Number Generators for Cryptography: Design and Evaluation

Lecture Notes in Electrical Engineering, 2021

Research paper thumbnail of Power analysis attack resistable hardware cryptographical circuit design using reversible logic gate in quantum cellular automata

Microsystem Technologies, 2019

Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power ... more Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

Research paper thumbnail of Design and Comparative Analysis of Low-Power, High-Speed, 3-Bit Flash ADC for Biomedical Signal Processing Using 45-nm CMOS Technology

Computational Advancement in Communication Circuits and Systems, 2019

The analog-to-digital converter is the key component for communication and signal processing. Thi... more The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.

Research paper thumbnail of Novel True Random Number Generator Based Hardware Cryptographic Architecture Using Quantum-Dot Cellular Automata

International Journal of Theoretical Physics, 2019

Information processing and conventional computing are usually resource constrained; evermore they... more Information processing and conventional computing are usually resource constrained; evermore they need to operate in a physically suspicious environment. Consequently, communication architectures, protocol and its security aspects have been the focus of many recent research works. Our proposal demonstrates how to amend this vulnerable circumstance through a three-stage security scheme in quantum-dot cellular automata (QCA) based nanoarchitecture. The primary objective of this hardware-based cryptographic architecture using QCA is to intend a distinctly secure communication architecture comprising less number of QCA cells, which enchant the comparative performance investigation along with the powerarea constraints. In our proposed design the random bits are extorted from an asymmetrically arranged crossed loop TRNG where the seed circuits are used to boost the volatility of initiated number sequences as well as the distinction of the random numbers. In this work, a novel encryption-decryption prototype for a secure communication system has been implemented. The simulation results are obtained from QCADesigner tool v2.0.3, which fruitfully agreed with the industry standard. An intact evaluation of the proposed TRNG and the comparative analysis with a recent work of TRNG has been authorized by the 7.79% improvements in average energy dissipation for different Kink energy ratio. Altogether the proposed architecture and its contemporary implementation in QCA framework can be recognized by means of the advantages in 7.02% circuit complexity, 11.53% area, and 13.77% average leakage power dissipation with respect to the recent work of TRNG. Thus our proposed novel TRNG based hardware cryptographic architecture can be considered as a potential next-generation networkon-chip (NoC) realization for a large-scale cryptosystem in QCA technology.

Research paper thumbnail of Design of Two Stage Ultra Low Power CMOS Operational Transconductance Amplifier(OTA) Using 180 nm Technology

International journal of advanced research in electrical, electronics and instrumentation engineering, 2016

This paper deals with well-defined design criteria for ultra low power two stage CMOS operational... more This paper deals with well-defined design criteria for ultra low power two stage CMOS operational transconductance amplifiers (OTAs) with simple yet robust implementation in nm dimension. A simple design approach which allows electrical parameters to be univocally related to each circuit element and biasing values for low frequency applications is presented.The operational transconductance amplifier with ±1.8v power supply has been simulated using TANNER Tools ver.13 with 0.18μm CMOS technology which provide expected characteristics with convenient performance for given specification.

Research paper thumbnail of Quantum Random Number Generators for Cryptography: Design and Evaluation

Lecture Notes in Electrical Engineering

Research paper thumbnail of Impacts of COVID-19: A Comprehensive Study Using Linear Regression Analysis in a Predictive Approach

Lecture Notes in Electrical Engineering

Research paper thumbnail of Novel True Random Number Generator Based Hardware Cryptographic Architecture Using Quantum-Dot Cellular Automata

International Journal of Theoretical Physics

Information processing and conventional computing are usually resource constrained; evermore they... more Information processing and conventional computing are usually resource constrained; evermore they need to operate in a physically suspicious environment. Consequently, communication architectures, protocol and its security aspects have been the focus of many recent research works. Our proposal demonstrates how to amend this vulnerable circumstance through a three-stage security scheme in quantum-dot cellular automata (QCA) based nano-architecture. The primary objective of this hardware-based cryptographic architecture using QCA is to intend a distinctly secure communication architecture comprising less number of QCA cells, which enchant the comparative performance investigation along with the power-area constraints. In our proposed design the random bits are extorted from an asymmetrically arranged crossed loop TRNG where the seed circuits are used to boost the volatility of initiated number sequences as well as the distinction of the random numbers. In this work, a novel encryption-decryption prototype for a secure communication system has been implemented. The simulation results are obtained from QCADesigner tool v2.0.3, which fruitfully agreed with the industry standard. An intact evaluation of the proposed TRNG and the comparative analysis with a recent work of TRNG has been authorized by the 7.79% improvements in average energy dissipation for different Kink energy ratio. Altogether the proposed architecture and its contemporary implementation in QCA framework can be recognized by means of the advantages in 7.02% circuit complexity, 11.53% area, and 13.77% average leakage power dissipation with respect to the recent work of TRNG. Thus our proposed novel TRNG based hardware cryptographic architecture can be considered as a potential next-generation network-on-chip (NoC) realization for a large-scale cryptosystem in QCA technology.

Research paper thumbnail of Power analysis attack resistable hardware cryptographical circuit design using reversible logic gate in quantum cellular automata

Microsystem Technologies

Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power ... more Quantum-dot cellular automata (QCA) technology leads to rapid high-density combinatory low power exploitation to realize the reversible logic circuit in the nanoscale era. Reversible logic is an alternative to overcome excess energy indulgence of irreversible process. This paper illustrates a cost-effective, energy-efficient Universal Reversible Logic Gate in QCA framework which is capable of designing power analysis attack resistable hardware cryptographical circuit. The proposed (URLGs: U1 and U2) has been tested with simulator QCADesigner V2.0.3, outshined the existing pattern relating to the area, gate count, garbage count, and quantum cost. We found 37.5% garbage minimization is achieved compared to NFT, which is utmost minimization of garbage ever reported in QCA literature. Thirteen three variable standard Boolean functions are considered as logic benchmarks to guesstimate the capability and efficiency of proposed URLG in QCA circuit implementation and synthesizing logic gates. In average, our proposed U2 achieved 36.66% improvement in energy dissipation for different kink energy ratios over early reported work.

Research paper thumbnail of Electrical Characteristics of MESFET Using GaAs, InP and GaN as Substrates

Lecture Notes in Electrical Engineering, 2015

Research paper thumbnail of VLSI Adder Implementation Using Generalized Ling Algorithm

Several addition algorithms are developed to improve speed of addition by manipulating the equati... more Several addition algorithms are developed to improve speed of addition by manipulating the equations used for sum and carry. As with increase in speed of carry and sum computation, the time required for all mathematical calculation in a digital system can be reduced. Carry Look Ahead Adder calculates carry signals in advance based on input signal but carry calculation becomes complex beyond 4 bits. CLA is implemented in three stages; pre-processing, carry generation and parallel addition. Ling Adder is a special kind of CLA Adders. The improvement is in the carry generation stage which is the most intensive one. i.e. pseudo carry h i = c i + c i-1 is propagated instead of c i . Hardware implemented using Ling's algorithm is speedier than Carry Look Ahead adder. These expressions were modified by Ling, reducing complexity of carry generation but at the cost of sum generation complexity. However the total time for addition process is quite less than normal CLA. Ling's algorithm is hardware specific i.e. hardware derived for n bits is specific for it. The implementation differs for every n bit adder. Here hardware specific Ling Adder is transformed to general purpose Ling adder. Proposed adder is based on generalized Ling's algorithm where delay will be same for all addition process. In this thesis, 4,8,16,32 and 64 bit adders for CLA and Ling algorithm is implemented and the time delay, throughput and utilization was compared between two adders.