Quang Dinh - Academia.edu (original) (raw)

Papers by Quang Dinh

This paper aims to develop an engine start control approach for a micro/mild hybrid machine for a... more This paper aims to develop an engine start control approach for a micro/mild hybrid machine for a capable of cranking the engine without injection. First, the powertrain is physically modelled using a co-simulation platform. Second, experiment data of the traditional machine is acquired to optimize the model. Third, a model-based adaptive controller is designed for the starter to crank the engine quickly and smoothly to minimize the operator discomfort. The effectiveness of the proposed approach is validated through numerical simulations with the established model.

Boleophthalmus boddarti (Pallas, 1770) is one of mudskippers (Gobiidae), and a potential commerci... more Boleophthalmus boddarti (Pallas, 1770) is one of mudskippers (Gobiidae), and a potential commercial fish in Mekong Delta, Vietnam. The study on the goby B. boddarti was investigated in Tran De district, Soc Trang province, Mekong Delta, Vietnam, to establish some basic population biology parameters. A total of 117 individuals were caught in mudflats of Tran De beach by deep net to determine length-weight relationships of this species. After determining sex by external features, total length (TL in cm), and body weight (W in g) of this goby were measured. This study ran for six months, from January 2013 to June 2013. The mean lengths of female significantly differed from value of male, whereas the average body weights of male and female were quite similar. The proportion of male and female groups were not substantially different. The length-weight relationships of total fish, male and female were highly correlated with high regression values which were 0.813, 0.866 and 0.767, respect...

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010

Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal tra... more Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow glitches consume less power than wide glitches. Glitch width and transition density modeling is further complicated by the effect of process variation. This paper presents a fast and accurate dynamic power estimation method that considers the detailed effect of process variation. First, we extend the probabilistic modeling approach to handle timing variations. Then the power consumption of a logic gate is computed based on the transition waveforms of its inputs. Both mean values and standard deviations of the dynamic power are estimated with high confidence based on accurate device characterization data. Compared with SPICE-based Monte Carlo simulations for small circuits, our power estimator reports power results within 3% error for the mean and 5% error for the standard deviation with six orders of magnitude speedup. For medium and large benchmarks, it is impossible to run Monte Carlo simulations with enough samples due to very long runtime, while our estimator can finish within minutes.

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, 2008

Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custo... more Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases.

2010 IEEE International Conference on Computer Design, 2010

As advances in process technology continue to scale down transistors, low power design is becomin... more As advances in process technology continue to scale down transistors, low power design is becoming more critical. Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching. In this paper, we consider finegrained clock gating through pipelining, in which control signals from one pipeline stage are used to freeze some logic in the next pipeline stage. We present a novel BDD-based decomposition algorithm to restructure the circuit and expose possible control signals that would maximize power saving. We then use ILP formulation to select the optimal set of control signals for the circuit. We show that the constraint matrix is totally unimodular, and solve this selection problem optimally using linear programming. Comparing to a previous work [7], we get similar and 9% better dynamic power saving for small and medium circuits, respectively. For the largest MCNC circuits, which the previous technique cannot handle, we get an average of 19% dynamic power saving with 9.3% area overhead comparing to the original, non-restructured circuits.

This paper aims to develop an engine start control approach for a micro/mild hybrid machine for a... more This paper aims to develop an engine start control approach for a micro/mild hybrid machine for a capable of cranking the engine without injection. First, the powertrain is physically modelled using a co-simulation platform. Second, experiment data of the traditional machine is acquired to optimize the model. Third, a model-based adaptive controller is designed for the starter to crank the engine quickly and smoothly to minimize the operator discomfort. The effectiveness of the proposed approach is validated through numerical simulations with the established model.

Boleophthalmus boddarti (Pallas, 1770) is one of mudskippers (Gobiidae), and a potential commerci... more Boleophthalmus boddarti (Pallas, 1770) is one of mudskippers (Gobiidae), and a potential commercial fish in Mekong Delta, Vietnam. The study on the goby B. boddarti was investigated in Tran De district, Soc Trang province, Mekong Delta, Vietnam, to establish some basic population biology parameters. A total of 117 individuals were caught in mudflats of Tran De beach by deep net to determine length-weight relationships of this species. After determining sex by external features, total length (TL in cm), and body weight (W in g) of this goby were measured. This study ran for six months, from January 2013 to June 2013. The mean lengths of female significantly differed from value of male, whereas the average body weights of male and female were quite similar. The proportion of male and female groups were not substantially different. The length-weight relationships of total fish, male and female were highly correlated with high regression values which were 0.813, 0.866 and 0.767, respect...

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010

Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal tra... more Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow glitches consume less power than wide glitches. Glitch width and transition density modeling is further complicated by the effect of process variation. This paper presents a fast and accurate dynamic power estimation method that considers the detailed effect of process variation. First, we extend the probabilistic modeling approach to handle timing variations. Then the power consumption of a logic gate is computed based on the transition waveforms of its inputs. Both mean values and standard deviations of the dynamic power are estimated with high confidence based on accurate device characterization data. Compared with SPICE-based Monte Carlo simulations for small circuits, our power estimator reports power results within 3% error for the mean and 5% error for the standard deviation with six orders of magnitude speedup. For medium and large benchmarks, it is impossible to run Monte Carlo simulations with enough samples due to very long runtime, while our estimator can finish within minutes.

Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, 2008

Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custo... more Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. In this paper, we investigate two techniques to improve these flows, so that ASIP can be efficiently applied to simple computer architectures in embedded applications. Firstly, we efficiently generate custom instructions with multi-cycle IO (which allows multi-outputs), thus removing the constraint imposed by the ports of the register file. Secondly, we allow identical portions of different custom instructions to be shared, thus allowing more custom instructions under the same area constraint. To handle the greatly increased exploration space, we propose several heuristics to keep the problem tractable. Experimental results show that we can achieve 3x speedup in some cases.

2010 IEEE International Conference on Computer Design, 2010

As advances in process technology continue to scale down transistors, low power design is becomin... more As advances in process technology continue to scale down transistors, low power design is becoming more critical. Clock gating is a dynamic power saving technique that can freeze some flip-flops and prevent portion of the circuit from unneeded switching. In this paper, we consider finegrained clock gating through pipelining, in which control signals from one pipeline stage are used to freeze some logic in the next pipeline stage. We present a novel BDD-based decomposition algorithm to restructure the circuit and expose possible control signals that would maximize power saving. We then use ILP formulation to select the optimal set of control signals for the circuit. We show that the constraint matrix is totally unimodular, and solve this selection problem optimally using linear programming. Comparing to a previous work [7], we get similar and 9% better dynamic power saving for small and medium circuits, respectively. For the largest MCNC circuits, which the previous technique cannot handle, we get an average of 19% dynamic power saving with 9.3% area overhead comparing to the original, non-restructured circuits.