Raja Mahmou - Academia.edu (original) (raw)

Papers by Raja Mahmou

Research paper thumbnail of Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

arXiv (Cornell University), Mar 15, 2012

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

Cornell University - arXiv, Mar 15, 2012

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of CMOS Technology Dedicated to Low Power Consumption Wireless Applications

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of A Low Power Consumption Gilbert-Cell Mixer in 65 nm CMOS Technology

In this work, we present a design and simulation of low power consumption down conversion Gilbert... more In this work, we present a design and simulation of low power consumption down conversion Gilbert-Cell mixer, in the 1.9 GHz wireless application. The circuit is in a 65 nm – CMOS technology at a supply voltage of 1.8 V. The obtained results show a third order input intercept point (IIP3) and a Noise Figure in the order of 1.7 dBm and 3.13 dB respectively, when the conversion gain equal to 13.97 dB, and a power consumed equal to 2mW. These performances justify a Low power, Low Noise and an acceptable Linearity of this mixer compared to others approaches found in the literature.

Research paper thumbnail of A 65-NM CMOS RF Mixer for Different Applications

A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consum... more A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.

Research paper thumbnail of High linearity, low power RF mixer design in 65nm CMOS technology

AEU - International Journal of Electronics and Communications, 2014

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1... more A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.

Research paper thumbnail of Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

arXiv (Cornell University), Mar 15, 2012

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications

Cornell University - arXiv, Mar 15, 2012

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of CMOS Technology Dedicated to Low Power Consumption Wireless Applications

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technolo... more The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

Research paper thumbnail of A Low Power Consumption Gilbert-Cell Mixer in 65 nm CMOS Technology

In this work, we present a design and simulation of low power consumption down conversion Gilbert... more In this work, we present a design and simulation of low power consumption down conversion Gilbert-Cell mixer, in the 1.9 GHz wireless application. The circuit is in a 65 nm – CMOS technology at a supply voltage of 1.8 V. The obtained results show a third order input intercept point (IIP3) and a Noise Figure in the order of 1.7 dBm and 3.13 dB respectively, when the conversion gain equal to 13.97 dB, and a power consumed equal to 2mW. These performances justify a Low power, Low Noise and an acceptable Linearity of this mixer compared to others approaches found in the literature.

Research paper thumbnail of A 65-NM CMOS RF Mixer for Different Applications

A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consum... more A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.

Research paper thumbnail of High linearity, low power RF mixer design in 65nm CMOS technology

AEU - International Journal of Electronics and Communications, 2014

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1... more A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.