Reinhard von Hanxleden - Academia.edu (original) (raw)

Papers by Reinhard von Hanxleden

Research paper thumbnail of Building timing predictable embedded systems

ACM Transactions on Embedded Computing Systems, 2014

Saarland Univ., 5: Uppsala Univ., 6: TU Dortmund, 7: Univ. of Toulouse, 8: CAU Kiel A large class... more Saarland Univ., 5: Uppsala Univ., 6: TU Dortmund, 7: Univ. of Toulouse, 8: CAU Kiel A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this paper is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

Research paper thumbnail of Model Engineering using Multimodeling ?

We study the simultaneous use of multiple modeling tech- niques in the design of embedded systems... more We study the simultaneous use of multiple modeling tech- niques in the design of embedded systems. We begin with a pre-existing Statecharts model of a simple case study, a trac light for a pedestrian crossing, using it to illustrate the need for multimodeling and the pit- falls. The original model combines two distinct models of computation (MoCs), nite state machines

Research paper thumbnail of Just model! — Putting automatic synthesis of node-link-diagrams into practice

2013 IEEE Symposium on Visual Languages and Human Centric Computing, 2013

ABSTRACT Node-link-diagrams can effectively communicate information, but their creation and maint... more ABSTRACT Node-link-diagrams can effectively communicate information, but their creation and maintenance require a lot of manual effort. Therefore we follow the transient views approach that aims at automatically deriving high quality diagrams from arbitrary models. Besides composing diagram structures, this task involves the arrangement of the diagram elements on the canvas, and, on a finer-grained level of detail, the arrangement of the shapes (rectangles, circles, lines, etc.) that form the diagram elements. We show the feasibility of this approach by means of the Kieler Lightweight Diagrams (KLighD) framework that creates diagrams this way. We discuss our overall design objectives in terms of this framework, investigate an alternative way to shape diagram figures, and briefly demonstrate the usage of KLighD in custom modeling environments by means of a case study.

Research paper thumbnail of On the Pragmatics of Model-Based Design

Lecture Notes in Computer Science, 2010

The pragmatics of model-based design refers to the practical aspects of handling graphical system... more The pragmatics of model-based design refers to the practical aspects of handling graphical system models. This encompasses a range of activities, such as editing, browsing or simulating models. We believe that the pragmatics of modeling deserves more attention than is has received so far. We also believe that there is the potential for significant productivity enhancements, using technology that is largely already available. A key enabler here is the capability to automatically and quickly compute the layout of a graphical model, which frees the designer from the burden of manual drawing. This capability also allows to compute customized view of a model on the fly, which offers new possibilities for interactive browsing and for simulation.

Research paper thumbnail of Taming Graphical Modeling

Lecture Notes in Computer Science, 2010

Visual models help to understand complex systems. However, with the user interaction paradigms es... more Visual models help to understand complex systems. However, with the user interaction paradigms established today, activities such as creating, maintaining or browsing visual models can be very tedious. Valuable engineering time is wasted with archaic activities such as manual placement and routing of nodes and edges. This paper presents an approach to enhance productivity by focusing on the pragmatics of model-based design. Our contribution is twofold: First, the concept of meta layout enables the synthesis of different diagrammatic views on graphical models. This modularly employs sophisticated layout algorithms, closing the gap between MDE and graph drawing theory. Second, a view management logic harnesses this auto-layout to present customized views on models. These concepts have been implemented in the open source Kiel Integrated Environment for Layout Eclipse Rich Client (KIELER). Two applications-editing and simulation-illustrate how view management helps to increase developer productivity and tame model complexity.

Research paper thumbnail of Mapping esterel onto a multi-threaded embedded processor

ACM SIGOPS Operating Systems Review, 2006

The synchronous language Esterel is well-suited for programming control-dominated reactive system... more The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.

Research paper thumbnail of Towards Interactive Timing Analysis for Designing Reactive Systems

Reactive systems are increasingly developed using high-level modeling tools. Such modeling tools ... more Reactive systems are increasingly developed using high-level modeling tools. Such modeling tools may facilitate formal reasoning about concurrent programs, but provide little help when timing-related problems arise and deadlines are missed when running a real system. In these cases, the modeler has typically no information about timing properties and costly parts of the model; there is little or no guidance on how to improve the timing characteristics of the model. In this paper, we propose a design methodology where interactive timing analysis is an integral part of the modeling process. This methodology concerns how to aggregate timing values in a user-friendly manner and how to define timing analysis requests. We also introduce and formalize a new timing analysis interface that is designed for communicating timing information between a high-level modeling tool and a lower-level timing analysis tool.

Research paper thumbnail of Multithreaded Reactive Programming - the Kiel Esterel Processor

The Kiel Esterel Processor (KEP) is a multi-threaded reactive processor designed for the executio... more The Kiel Esterel Processor (KEP) is a multi-threaded reactive processor designed for the execution of programs written in the synchronous language Esterel. Design goals were timing predictability, minimal resource usage, and compliance to full Esterel V5. The KEP directly supports Esterel's reactive control flow operators, notably concurrency and various types of preemption, through dedicated control units. Esterel allows arbitrary combinations and nestings of these operators, which poses particular implementation challenges that are addressed here. Other notable features of the KEP are a refined instruction set architecture, which allows to trade off generality against resource usage, and a Tick Manager that minimizes reaction time jitter and can detect timing overruns.

Research paper thumbnail of Entwurf einer domänenspezifischen Sprache für elektronische Stellwerke

Die Entwicklung elektronischer Stellwerke für den Bahnbetrieb ist ein aufwändiges Unterfangen, we... more Die Entwicklung elektronischer Stellwerke für den Bahnbetrieb ist ein aufwändiges Unterfangen, welches sich besonders für die zahlreichen Nebenstrecken und andere kleinere Bahnanlagen häufig als unrentabel erweist. Um in Zukunft einerseits mehr Verkehr auf die Schiene zu bringen und zudem die Kosten für den Betrieb der Infrastruktur zu senken, müssen die Hardware-Komponenten günstiger werden, aber auch die Entwicklung der darauf laufenden Software produktiver erfolgen, ohne Abstriche bei der Sicherheit zu machen. Bisher werden für elektronische Stellwerke Prozessrechner eingesetzt, welche speziell auf das jeweilige Stellwerk zugeschnitten sind. Ebenso wird die Software speziell für die jeweilige Anlage entwickelt. Beide Komonenten müssen für den Betrieb zugelassen werden. Unser Ansatz zur Produktivitätssteigerung setzt einerseits auf den Einsatz standardisierter Hardware-Komponenten aus der Industrieautomation, hier konkret speicherprogrammierbarer Steuerungen, und andererseits auf ...

Research paper thumbnail of Denotational fixed-point semantics for constructive scheduling of synchronous concurrency

Acta Informatica, 2015

ABSTRACT The synchronous model of concurrent computation (SMoCC) is well established for programm... more ABSTRACT The synchronous model of concurrent computation (SMoCC) is well established for programming languages in the domain of safety-critical reactive and embedded systems. Translated into mainstream C/Java programming, the SMoCC corresponds to a cyclic execution model in which concurrent threads are synchronised on a logical clock that cuts system computation into a sequence of macro-steps. A causality analysis verifies the existence of a schedule on memory accesses to ensure each macro-step is deadlock-free and determinate. We introduce an abstract semantic domain \(I(\mathbb {D}, \mathbb {P})\) and an associated denotational fixed-point semantics for reasoning about concurrent and sequential variable accesses within a synchronous cycle-based model of computation. We use this domain for a new and extended behavioural definition of Berry’s causality analysis in terms of approximation intervals. The domain \(I(\mathbb {D}, \mathbb {P})\) extends the domain \(I(\mathbb {D})\) from our previous work and fixes a mistake in the treatment of initialisations. Based on this fixed-point semantics we propose the notion of Input Berry-constructiveness (IBC) for synchronous programs. This new IBC class lies properly between strong (SBC) and normal Berry-constructiveness (BC) defined in previous work. SBC and BC are two ways to interpret the standard constructive semantics of synchronous programming, as exemplified by imperative SMoCC languages such as Esterel or Quartz. SBC is often too restrictive as it requires all variables to be initialised by the program. BC can be too permissive because it initialises all variables to a fixed value, by default. Where the initialisation happens through the memory, e.g., when carrying values from one synchronous tick to the next, then IBC is more appropriate. IBC links two levels of execution, the macro-step level and the micro-step level. We prove that the denotational fixed-point analysis for IBC, and hence Berry’s causality analysis, is sound with respect to operational micro-level scheduling. The denotational model can thus be viewed as a compositional presentation of a synchronous scheduling strategy that ensures reactiveness and determinacy for imperative concurrent programming.

Research paper thumbnail of Compiler Analysis for Irregular Problems in Fortran D

We developed a dataflow framework which provides abasis for rigorously defining strategies to mak... more We developed a dataflow framework which provides abasis for rigorously defining strategies to make use ofruntime preprocessing methods for distributed memorymultiprocessors.In many programs, several loops access the same offprocessormemory locations. Our runtime support givesus a mechanism for tracking and reusing copies of offprocessordata. A key aspect of our compiler analysisstrategy is to determine when it is safe to reuse copiesof off-processor data. Another crucial function of...

Research paper thumbnail of Grounding Synchronous Deterministic Concurrency in Sequential Programming

Lecture Notes in Computer Science, 2014

ABSTRACT Using a new domain-theoretic characterisation we show that Berry’s constructive semantic... more ABSTRACT Using a new domain-theoretic characterisation we show that Berry’s constructive semantics is a conservative approximation of the recently proposed sequentially constructive (SC) model of computation. We prove that every Berry-constructive program is deterministic and deadlock-free under sequentially admissible scheduling. This gives, for the first time, a natural interpretation of Berry-constructiveness for shared-memory, multi-threaded programming in terms of synchronous cycle-based scheduling, where previous results were cast in terms of synchronous circuits. This opens the door to a direct mapping of Esterel’s signal mechanism into boolean variables that can be set and reset under the programmer’s control within a tick. We illustrate the practical usefulness of this mapping by discussing how signal reincarnation is handled efficiently by this transformation, which is of linear complexity in program size, in contrast to earlier techniques that had quadratic overhead.

Research paper thumbnail of Port Constraints in Hierarchical Layout of Data Flow Diagrams

Lecture Notes in Computer Science, 2010

Research paper thumbnail of Automatic layout in the face of unattached comments

2014 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2014

ABSTRACT Visual languages based on node-link diagrams are widely used for systems modeling. As in... more ABSTRACT Visual languages based on node-link diagrams are widely used for systems modeling. As in textual languages, comments can make diagrams easier to understand. In the absence of an explicit attachment between comments and the diagram elements they relate to, that relationship is usually given implicitly by the manual placement of comments near the related elements. While algorithms for the automatic layout of diagrams can make working with diagrams more effective, they usually fail to preserve implicit attachments by placing comments at arbitrary positions. In this paper, we propose a comment attachment algorithm that extracts implicit attachments and makes them accessible to layout algorithms. We implemented the algorithm in an application for browsing Ptolemy diagrams and achieved success rates, i. e. attachments as intended by the user, of up to 90 %.

Research paper thumbnail of Two applications for transient views in software development environments

2014 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2014

ABSTRACT Pragmatics-aware modeling refers to model-driven engineering with designer productivity ... more ABSTRACT Pragmatics-aware modeling refers to model-driven engineering with designer productivity in mind. We apply this concept to traditional software development by introducing two exemplary applications for transient views geared at increasing developer productivity: UML class diagram generation and debug state visualization.

Research paper thumbnail of KIELER: Building on automatic layout for pragmatics-aware modeling

2013 IEEE Symposium on Visual Languages and Human Centric Computing, 2013

ABSTRACT Automatic layout is a key enabler for pragmatics-aware modeling, which refers to model-d... more ABSTRACT Automatic layout is a key enabler for pragmatics-aware modeling, which refers to model-driven engineering with designer productivity in mind. This showpiece introduces an infrastructure for the integration of graph layout libraries and their configuration with regard to graphical views of modeling applications.

Research paper thumbnail of Light-weight Synchronous Java (SJL): An approach for programming deterministic reactive systems with Java

Computing, 2014

ABSTRACT A key issue in the development of reliable embedded software is the proper handling of r... more ABSTRACT A key issue in the development of reliable embedded software is the proper handling of reactive control-flow, which typically involves concurrency. Java and its thread concept have only limited provisions for implementing deterministic concurrency. Thus, as has been observed in the past, it is challenging to develop concurrent Java programs without any deadlocks or race conditions. To alleviate this situation, the Light-weight Synchronous Java (SJL) approach presented here adopts the key concepts that have been established in the world of synchronous programming for handling reactive control-flow. Thus SJL not only provides deterministic concurrency, but also different variants of deterministic preemption. Furthermore SJL allows concurrent threads to communicate with Esterel-style signals. As a case study for an embedded system usage, we also report on how the SJL concepts have been ported to the ARM-based Lego Mindstorms NXT system. We evaluated the SJL approach to be efficient and provide experimental results comparing it to Java threads.

Research paper thumbnail of Improved Layout for Data Flow Diagrams with Port Constraints

Lecture Notes in Computer Science, 2012

ABSTRACT The automatic generation of graphical views for data flow models and the efficient devel... more ABSTRACT The automatic generation of graphical views for data flow models and the efficient development of such models require layout algorithms that are able to handle their specific requirements. Examples include constraints on the placement of ports as well as the proper handling of nested models. We present an algorithm for laying out data flow diagrams that improves earlier approaches by reducing the number of edge crossings and bend points. We validate the quality of our algorithm with a range of models drawn from Ptolemy, a popular modeling tool for the design of embedded systems.

Research paper thumbnail of Slicing analysis and indirect accesses to distributed arrays

Lecture Notes in Computer Science, 1994

Research paper thumbnail of SCCharts: sequentially constructive statecharts for safety-critical applications

ACM SIGPLAN Notices, 2014

ABSTRACT We present a new visual language, SCCharts, designed for specifying safety-critical reac... more ABSTRACT We present a new visual language, SCCharts, designed for specifying safety-critical reactive systems. SCCharts use a statechart notation and provide determinate concurrency based on a synchronous model of computation (MoC), without restrictions common to previous synchronous MoCs. Specifically, we lift earlier limitations on sequential accesses to shared variables, by leveraging the sequentially constructive MoC. The semantics and key features of SCCharts are defined by a very small set of elements, the Core SCCharts, consisting of state machines plus fork/join concurrency. We also present a compilation chain that allows efficient synthesis of software and hardware.

Research paper thumbnail of Building timing predictable embedded systems

ACM Transactions on Embedded Computing Systems, 2014

Saarland Univ., 5: Uppsala Univ., 6: TU Dortmund, 7: Univ. of Toulouse, 8: CAU Kiel A large class... more Saarland Univ., 5: Uppsala Univ., 6: TU Dortmund, 7: Univ. of Toulouse, 8: CAU Kiel A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori. Perhaps paradoxically, this problem has become more difficult by the introduction of performanceenhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this paper is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of "predictability", and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

Research paper thumbnail of Model Engineering using Multimodeling ?

We study the simultaneous use of multiple modeling tech- niques in the design of embedded systems... more We study the simultaneous use of multiple modeling tech- niques in the design of embedded systems. We begin with a pre-existing Statecharts model of a simple case study, a trac light for a pedestrian crossing, using it to illustrate the need for multimodeling and the pit- falls. The original model combines two distinct models of computation (MoCs), nite state machines

Research paper thumbnail of Just model! — Putting automatic synthesis of node-link-diagrams into practice

2013 IEEE Symposium on Visual Languages and Human Centric Computing, 2013

ABSTRACT Node-link-diagrams can effectively communicate information, but their creation and maint... more ABSTRACT Node-link-diagrams can effectively communicate information, but their creation and maintenance require a lot of manual effort. Therefore we follow the transient views approach that aims at automatically deriving high quality diagrams from arbitrary models. Besides composing diagram structures, this task involves the arrangement of the diagram elements on the canvas, and, on a finer-grained level of detail, the arrangement of the shapes (rectangles, circles, lines, etc.) that form the diagram elements. We show the feasibility of this approach by means of the Kieler Lightweight Diagrams (KLighD) framework that creates diagrams this way. We discuss our overall design objectives in terms of this framework, investigate an alternative way to shape diagram figures, and briefly demonstrate the usage of KLighD in custom modeling environments by means of a case study.

Research paper thumbnail of On the Pragmatics of Model-Based Design

Lecture Notes in Computer Science, 2010

The pragmatics of model-based design refers to the practical aspects of handling graphical system... more The pragmatics of model-based design refers to the practical aspects of handling graphical system models. This encompasses a range of activities, such as editing, browsing or simulating models. We believe that the pragmatics of modeling deserves more attention than is has received so far. We also believe that there is the potential for significant productivity enhancements, using technology that is largely already available. A key enabler here is the capability to automatically and quickly compute the layout of a graphical model, which frees the designer from the burden of manual drawing. This capability also allows to compute customized view of a model on the fly, which offers new possibilities for interactive browsing and for simulation.

Research paper thumbnail of Taming Graphical Modeling

Lecture Notes in Computer Science, 2010

Visual models help to understand complex systems. However, with the user interaction paradigms es... more Visual models help to understand complex systems. However, with the user interaction paradigms established today, activities such as creating, maintaining or browsing visual models can be very tedious. Valuable engineering time is wasted with archaic activities such as manual placement and routing of nodes and edges. This paper presents an approach to enhance productivity by focusing on the pragmatics of model-based design. Our contribution is twofold: First, the concept of meta layout enables the synthesis of different diagrammatic views on graphical models. This modularly employs sophisticated layout algorithms, closing the gap between MDE and graph drawing theory. Second, a view management logic harnesses this auto-layout to present customized views on models. These concepts have been implemented in the open source Kiel Integrated Environment for Layout Eclipse Rich Client (KIELER). Two applications-editing and simulation-illustrate how view management helps to increase developer productivity and tame model complexity.

Research paper thumbnail of Mapping esterel onto a multi-threaded embedded processor

ACM SIGOPS Operating Systems Review, 2006

The synchronous language Esterel is well-suited for programming control-dominated reactive system... more The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage.

Research paper thumbnail of Towards Interactive Timing Analysis for Designing Reactive Systems

Reactive systems are increasingly developed using high-level modeling tools. Such modeling tools ... more Reactive systems are increasingly developed using high-level modeling tools. Such modeling tools may facilitate formal reasoning about concurrent programs, but provide little help when timing-related problems arise and deadlines are missed when running a real system. In these cases, the modeler has typically no information about timing properties and costly parts of the model; there is little or no guidance on how to improve the timing characteristics of the model. In this paper, we propose a design methodology where interactive timing analysis is an integral part of the modeling process. This methodology concerns how to aggregate timing values in a user-friendly manner and how to define timing analysis requests. We also introduce and formalize a new timing analysis interface that is designed for communicating timing information between a high-level modeling tool and a lower-level timing analysis tool.

Research paper thumbnail of Multithreaded Reactive Programming - the Kiel Esterel Processor

The Kiel Esterel Processor (KEP) is a multi-threaded reactive processor designed for the executio... more The Kiel Esterel Processor (KEP) is a multi-threaded reactive processor designed for the execution of programs written in the synchronous language Esterel. Design goals were timing predictability, minimal resource usage, and compliance to full Esterel V5. The KEP directly supports Esterel's reactive control flow operators, notably concurrency and various types of preemption, through dedicated control units. Esterel allows arbitrary combinations and nestings of these operators, which poses particular implementation challenges that are addressed here. Other notable features of the KEP are a refined instruction set architecture, which allows to trade off generality against resource usage, and a Tick Manager that minimizes reaction time jitter and can detect timing overruns.

Research paper thumbnail of Entwurf einer domänenspezifischen Sprache für elektronische Stellwerke

Die Entwicklung elektronischer Stellwerke für den Bahnbetrieb ist ein aufwändiges Unterfangen, we... more Die Entwicklung elektronischer Stellwerke für den Bahnbetrieb ist ein aufwändiges Unterfangen, welches sich besonders für die zahlreichen Nebenstrecken und andere kleinere Bahnanlagen häufig als unrentabel erweist. Um in Zukunft einerseits mehr Verkehr auf die Schiene zu bringen und zudem die Kosten für den Betrieb der Infrastruktur zu senken, müssen die Hardware-Komponenten günstiger werden, aber auch die Entwicklung der darauf laufenden Software produktiver erfolgen, ohne Abstriche bei der Sicherheit zu machen. Bisher werden für elektronische Stellwerke Prozessrechner eingesetzt, welche speziell auf das jeweilige Stellwerk zugeschnitten sind. Ebenso wird die Software speziell für die jeweilige Anlage entwickelt. Beide Komonenten müssen für den Betrieb zugelassen werden. Unser Ansatz zur Produktivitätssteigerung setzt einerseits auf den Einsatz standardisierter Hardware-Komponenten aus der Industrieautomation, hier konkret speicherprogrammierbarer Steuerungen, und andererseits auf ...

Research paper thumbnail of Denotational fixed-point semantics for constructive scheduling of synchronous concurrency

Acta Informatica, 2015

ABSTRACT The synchronous model of concurrent computation (SMoCC) is well established for programm... more ABSTRACT The synchronous model of concurrent computation (SMoCC) is well established for programming languages in the domain of safety-critical reactive and embedded systems. Translated into mainstream C/Java programming, the SMoCC corresponds to a cyclic execution model in which concurrent threads are synchronised on a logical clock that cuts system computation into a sequence of macro-steps. A causality analysis verifies the existence of a schedule on memory accesses to ensure each macro-step is deadlock-free and determinate. We introduce an abstract semantic domain \(I(\mathbb {D}, \mathbb {P})\) and an associated denotational fixed-point semantics for reasoning about concurrent and sequential variable accesses within a synchronous cycle-based model of computation. We use this domain for a new and extended behavioural definition of Berry’s causality analysis in terms of approximation intervals. The domain \(I(\mathbb {D}, \mathbb {P})\) extends the domain \(I(\mathbb {D})\) from our previous work and fixes a mistake in the treatment of initialisations. Based on this fixed-point semantics we propose the notion of Input Berry-constructiveness (IBC) for synchronous programs. This new IBC class lies properly between strong (SBC) and normal Berry-constructiveness (BC) defined in previous work. SBC and BC are two ways to interpret the standard constructive semantics of synchronous programming, as exemplified by imperative SMoCC languages such as Esterel or Quartz. SBC is often too restrictive as it requires all variables to be initialised by the program. BC can be too permissive because it initialises all variables to a fixed value, by default. Where the initialisation happens through the memory, e.g., when carrying values from one synchronous tick to the next, then IBC is more appropriate. IBC links two levels of execution, the macro-step level and the micro-step level. We prove that the denotational fixed-point analysis for IBC, and hence Berry’s causality analysis, is sound with respect to operational micro-level scheduling. The denotational model can thus be viewed as a compositional presentation of a synchronous scheduling strategy that ensures reactiveness and determinacy for imperative concurrent programming.

Research paper thumbnail of Compiler Analysis for Irregular Problems in Fortran D

We developed a dataflow framework which provides abasis for rigorously defining strategies to mak... more We developed a dataflow framework which provides abasis for rigorously defining strategies to make use ofruntime preprocessing methods for distributed memorymultiprocessors.In many programs, several loops access the same offprocessormemory locations. Our runtime support givesus a mechanism for tracking and reusing copies of offprocessordata. A key aspect of our compiler analysisstrategy is to determine when it is safe to reuse copiesof off-processor data. Another crucial function of...

Research paper thumbnail of Grounding Synchronous Deterministic Concurrency in Sequential Programming

Lecture Notes in Computer Science, 2014

ABSTRACT Using a new domain-theoretic characterisation we show that Berry’s constructive semantic... more ABSTRACT Using a new domain-theoretic characterisation we show that Berry’s constructive semantics is a conservative approximation of the recently proposed sequentially constructive (SC) model of computation. We prove that every Berry-constructive program is deterministic and deadlock-free under sequentially admissible scheduling. This gives, for the first time, a natural interpretation of Berry-constructiveness for shared-memory, multi-threaded programming in terms of synchronous cycle-based scheduling, where previous results were cast in terms of synchronous circuits. This opens the door to a direct mapping of Esterel’s signal mechanism into boolean variables that can be set and reset under the programmer’s control within a tick. We illustrate the practical usefulness of this mapping by discussing how signal reincarnation is handled efficiently by this transformation, which is of linear complexity in program size, in contrast to earlier techniques that had quadratic overhead.

Research paper thumbnail of Port Constraints in Hierarchical Layout of Data Flow Diagrams

Lecture Notes in Computer Science, 2010

Research paper thumbnail of Automatic layout in the face of unattached comments

2014 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2014

ABSTRACT Visual languages based on node-link diagrams are widely used for systems modeling. As in... more ABSTRACT Visual languages based on node-link diagrams are widely used for systems modeling. As in textual languages, comments can make diagrams easier to understand. In the absence of an explicit attachment between comments and the diagram elements they relate to, that relationship is usually given implicitly by the manual placement of comments near the related elements. While algorithms for the automatic layout of diagrams can make working with diagrams more effective, they usually fail to preserve implicit attachments by placing comments at arbitrary positions. In this paper, we propose a comment attachment algorithm that extracts implicit attachments and makes them accessible to layout algorithms. We implemented the algorithm in an application for browsing Ptolemy diagrams and achieved success rates, i. e. attachments as intended by the user, of up to 90 %.

Research paper thumbnail of Two applications for transient views in software development environments

2014 IEEE Symposium on Visual Languages and Human-Centric Computing (VL/HCC), 2014

ABSTRACT Pragmatics-aware modeling refers to model-driven engineering with designer productivity ... more ABSTRACT Pragmatics-aware modeling refers to model-driven engineering with designer productivity in mind. We apply this concept to traditional software development by introducing two exemplary applications for transient views geared at increasing developer productivity: UML class diagram generation and debug state visualization.

Research paper thumbnail of KIELER: Building on automatic layout for pragmatics-aware modeling

2013 IEEE Symposium on Visual Languages and Human Centric Computing, 2013

ABSTRACT Automatic layout is a key enabler for pragmatics-aware modeling, which refers to model-d... more ABSTRACT Automatic layout is a key enabler for pragmatics-aware modeling, which refers to model-driven engineering with designer productivity in mind. This showpiece introduces an infrastructure for the integration of graph layout libraries and their configuration with regard to graphical views of modeling applications.

Research paper thumbnail of Light-weight Synchronous Java (SJL): An approach for programming deterministic reactive systems with Java

Computing, 2014

ABSTRACT A key issue in the development of reliable embedded software is the proper handling of r... more ABSTRACT A key issue in the development of reliable embedded software is the proper handling of reactive control-flow, which typically involves concurrency. Java and its thread concept have only limited provisions for implementing deterministic concurrency. Thus, as has been observed in the past, it is challenging to develop concurrent Java programs without any deadlocks or race conditions. To alleviate this situation, the Light-weight Synchronous Java (SJL) approach presented here adopts the key concepts that have been established in the world of synchronous programming for handling reactive control-flow. Thus SJL not only provides deterministic concurrency, but also different variants of deterministic preemption. Furthermore SJL allows concurrent threads to communicate with Esterel-style signals. As a case study for an embedded system usage, we also report on how the SJL concepts have been ported to the ARM-based Lego Mindstorms NXT system. We evaluated the SJL approach to be efficient and provide experimental results comparing it to Java threads.

Research paper thumbnail of Improved Layout for Data Flow Diagrams with Port Constraints

Lecture Notes in Computer Science, 2012

ABSTRACT The automatic generation of graphical views for data flow models and the efficient devel... more ABSTRACT The automatic generation of graphical views for data flow models and the efficient development of such models require layout algorithms that are able to handle their specific requirements. Examples include constraints on the placement of ports as well as the proper handling of nested models. We present an algorithm for laying out data flow diagrams that improves earlier approaches by reducing the number of edge crossings and bend points. We validate the quality of our algorithm with a range of models drawn from Ptolemy, a popular modeling tool for the design of embedded systems.

Research paper thumbnail of Slicing analysis and indirect accesses to distributed arrays

Lecture Notes in Computer Science, 1994

Research paper thumbnail of SCCharts: sequentially constructive statecharts for safety-critical applications

ACM SIGPLAN Notices, 2014

ABSTRACT We present a new visual language, SCCharts, designed for specifying safety-critical reac... more ABSTRACT We present a new visual language, SCCharts, designed for specifying safety-critical reactive systems. SCCharts use a statechart notation and provide determinate concurrency based on a synchronous model of computation (MoC), without restrictions common to previous synchronous MoCs. Specifically, we lift earlier limitations on sequential accesses to shared variables, by leveraging the sequentially constructive MoC. The semantics and key features of SCCharts are defined by a very small set of elements, the Core SCCharts, consisting of state machines plus fork/join concurrency. We also present a compilation chain that allows efficient synthesis of software and hardware.