Roy Paily - Academia.edu (original) (raw)
Papers by Roy Paily
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016
The main objective of this paper aims at designing an efficient blind assistance system for the v... more The main objective of this paper aims at designing an efficient blind assistance system for the visually impaired people using real time disparity estimation algorithm. The local window based matching algorithms known as sum of absolute differences (SAD) and zero-mean SAD (ZSAD) are used for the disparity estimation and efficient hardware architectures for those algorithms are implemented in FPGA. The SAD and ZSAD algorithms are implemented for the image resolution of 640x360 pixels with square window of size 8x8 pixels and with a disparity range of 0 to 99. An efficient line buffering scheme for the left and right window of the two camera images is implemented to support the parallel processing mechanism. To provide high frame rate per second (fps) to the artificial vision system, parallel processing architecture for disparity estimation is required, but it consumes huge amount of hardware resources which is not desirable for this application. So, semi-parallel architectures are implemented for SAD and ZSAD algorithms for a compromise between hardware resource utilization and speed. The FPGA resource utilization for the ZSAD and SAD algorithms for a frame rate of 30 fps are 43529 LUTs, 50144 FFs and 34548 LUTs, 37544 FFs respectively. ZSAD algorithm consumes around 30% more hardware resources compared to SAD, but to counter the randomized distortion caused by the non-ideal stereo cameras ZSAD is more preferred. Finally from the disparity, the distance of the nearest obstacle is estimated and blind person is alerted through audio device instructions.
2017 Devices for Integrated Circuit (DevIC)
In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on... more In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on the backbone of polymers of thiophene, selenophene and tellurophene and their hexyl derivatives by studying the effect on their molecular orbital structure at the B3LYP/6-31G level of theory. The effects on photovoltaic properties are also estimated using the well-established Scharber model to predict change in open-circuit voltage Voc when compared with P3HT which is a benchmark for such polymers. Fluorination was seen to increase predicted Voc in all cases whereas the Se and Te heteroatoms afforded a lower bandgap towards higher values of short-circuit current Jsc.
TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON)
In this paper, we present a new 10T design for static random access memory (SRAM). The proposed d... more In this paper, we present a new 10T design for static random access memory (SRAM). The proposed design simultaneously aims to address stability, power and half select issues. The design metrics such as power, delay, and stability of the proposed design are compared with 7T, 11T, and 9T SRAM cells. It is observed that the proposed design reduces read and write power by 27.69% and 41.72% as compared to 11T and 9T SRAM cell. Furthermore, WSNM of the proposed SRAM is larger as compared to 7T, 9T and 11T. In addition, the RSNM is larger than 7T and 9T. The simulation result confirms that the proposed design is effective for low power application.
Oxide reliability is a major concern for the thin gate oxides of future ULSI technology. For cont... more Oxide reliability is a major concern for the thin gate oxides of future ULSI technology. For controlled growth of ultra-thin oxide, it is necessary to carry out the gate oxidation at comparatively lower temperature. However, due to the increase of the weak spots and pinholes in the low temperature grown oxides, they exhibit poor dielectric strength, high leakage current and high interface trap densities. This paper proposes a method, which identifies the weak spots and repairs them by selective anodisation. After the thermal gate oxidation, during the anodisation, current flows only through the weak spots in the oxide. Anodic oxide therefore grows over these weak spots, improving the stability of the oxide. An improvement in electrical characteristics was observed in the gate oxides treated by anodic oxidation under optimized conditions.
IEEE Transactions on Circuits and Systems II: Express Briefs
Design of high-performance processors with very low power requirement is the primary goal of many... more Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm<sup>2</sup> area and <inline-formula> <tex-math notation="LaTeX">$17.36~\mu \text{W}$ </tex-math></inline-formula>/MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of <inline-formula> <tex-math notation="LaTeX">$19.75~\mu \text{W}$ </tex-math></inline-formula>/MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.
2017 Devices for Integrated Circuit (DevIC), 2017
In this work, we employed Density Functional Theory (DFT), to study the interactions between NO a... more In this work, we employed Density Functional Theory (DFT), to study the interactions between NO and CO with Ti-doped zigzag graphene nanoribbon (ZGNR) structures. Two types of doped structures are considered i.e. SV-ZGNR in which Ti replaces one carbon atom and DV-ZGNR replacing two adjacent carbon atoms. Our results indicate that doped ZGNR is better for gas adsorption as compared to already reported doped 2-D graphene sheet. Also between the two doped structures, DV-ZGNR is preferred over SV-ZGNR in terms of adsorption. The changes in the electronic structures after the adsorption can be seen in terms of changes in the Density of states. Our study suggests that Ti-doped ZGNR can have the potential to be the sensing platform for these gases.
In this paper, we discuss a simplified finite element method (FEM) simulation of surface acoustic... more In this paper, we discuss a simplified finite element method (FEM) simulation of surface acoustic wave (SAW) delay line hydrogen sensor using COMSOL Multiphysics. A delay line SAW sensor consists of a transmitting interdigital transducer (IDT) and a receiving IDT separated by a few wavelengths. In this paper, the number of degrees of freedom (DOF) to solve for the SAW delay line sensor model is minimized by providing periodic boundary conditions to the transmitting IDT, which is a one finger structure. Further a palladium thin film is coated over the delay line. The palladium film transforms to palladium hydride in the presence of hydrogen. This change in palladium properties are provided to the assumed thin film over the delay line. The time domain analysis of SAW sensor with and without the presence of hydrogen is performed and change in velocity of the SAW is observed.
In this work, design of Fractional-N Frequency Synthesizer using PLL has been investigated. The s... more In this work, design of Fractional-N Frequency Synthesizer using PLL has been investigated. The simulation is done in 0.18 μm CMOS technology with CADENCE tools using UMC foundry models. The different parts of synthesizer discussed in detail. Three different phase detector architectures are implemented. High speed TSPC DFF has designed to divide the frequency of GHz range. The prescalar is modified to have a delay of 80 ps only. For VCO, a multi layer inductor is used to save the area. The phase noise can be further reduced with a ΔΣ modulator in feedback loop. The designed frequency synthesizer targets RF applications like DVB-SH, WLAN, 802.11, bluetooth, cordless phones and remote control. Keyword: VCO, TSPC DFF, phase detector.
In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on... more In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on the backbone of polymers of thiophene, selenophene and tellurophene and their hexyl derivatives by studying the effect on their molecular orbital structure at the B3LYP/6-31G level of theory. The effects on photovoltaic properties are also estimated using the well-established Scharber model to predict change in open-circuit voltage Voc when compared with P3HT which is a benchmark for such polymers. Fluorination was seen to increase predicted Voc in all cases whereas the Se and Te heteroatoms afforded a lower bandgap towards higher values of short-circuit current Jsc.
Design of high-performance processors with very low power requirement is the primary goal of many... more Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm<sup>2</sup> area and <inline-formula> <tex-math notation="LaTeX">$17.36~\mu \text{W}$ </tex-math></inline-formula&...
This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalizatio... more This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalization technique for logarithmic maximum-a-posteriori-probability (LMAPP) algorithm. We have suggested a decoder architecture based on these techniques for high throughput application. Application-specific-integrated-circuit (ASIC) implementation of the proposed decoder is carried out in 90 nm complementary-metal-oxide-semiconductor (CMOS) process and it has achieved a throughput of 612 Mbps at a maximum clock frequency of 625 MHz with an energy efficiency of 0.1 nJ/bit. Functional verification of the implemented channel decoder is carried out using field-programmable gate-array (FPGA) which is interconnected with logic analyzer via high-speed-data-transfer card. Bit-error-rate (BER) performance of the implemented decoder has shown a coding loss of approximately 0.2 dB in comparison with the simulated BER values.
IEEE Transactions on Nanotechnology
This article describes the fabrication of Zinc Ferrite-Zinc oxide (ZFO-ZnO) heterostructure devic... more This article describes the fabrication of Zinc Ferrite-Zinc oxide (ZFO-ZnO) heterostructure devices and the various sensing schemes that can be exploited using the same. A solvothermal approach has been used for the synthesis of ZFO-ZnO heterostructures having different compositions. The investigation of magnetic and electric properties is performed by varying the ratio of Zn<inline-formula><tex-math notation="LaTeX">$^{2+}$</tex-math></inline-formula> and Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ions. These heterostructures show enhanced magnetization with (i) an increase in the concentration of Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ions and (ii) exposure to hydrogen (H<inline-formula><tex-math notation="LaTeX">$_2$</tex-math></inline-formula>) gas. These fine molar ratio adjustments in magnetism are engineered to obtain desirable sensing properties. We fabricated several two-terminal devices for the study of multiple sensing schemes. These devices demonstrated a linear current-voltage characteristic, with enhanced electrical resistance when the Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ion concentration is reduced. Keywords- Magnetic analysis, Zinc Ferrite-Zinc oxide, sensors, room temperature, heterostructures, tunability and nanotechnology
Materials Horizons
Here, an extremely water-repellent, abrasion tolerant and low-strain based motions/expressions de... more Here, an extremely water-repellent, abrasion tolerant and low-strain based motions/expressions detecting pattern interface having ultra-sensitivity (∼18 300 for applied strain of 0.2%) has been introduced through strategic use of 1,4-conjugate addition reaction.
IEEE Transactions on Electron Devices
This work explores the fabrication and characterization of an ionic liquid channel field effect t... more This work explores the fabrication and characterization of an ionic liquid channel field effect transistor (FET) incorporated within the trench structure on SiO<sub>2</sub>. The trench structure allows any liquid to be accommodated, thereby eliminating the mold creation on the device or the requirement for an intricate architecture to store liquid. For the fabrication of the trench, we followed a standard photolithography process with the help of selective etching of aluminum and SiO<sub>2</sub>. The fabricated trench surface is characterized using atomic force microscopy (AFM) and contact angle analysis. The electrical characterization of the proposed FET structure is also performed with 0.01-mM potassium chloride (KCl) solution as an ionic channel. We tested both the n-FET and p-FET type characteristics which can be controlled by the back gate biasing condition. The dc characterization shows a high <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio of 10<sup>5</sup> for both the n-FET and p-FET. The device further shows an improvement in K<sup>+</sup> mobility and Cl<sup>−</sup> mobility of <inline-formula> <tex-math notation="LaTeX">$2.24 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.96 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ </tex-math></inline-formula>, respectively. We also carried out the FET structure modeling to estimate the effective <inline-formula> <tex-math notation="LaTeX">${C}_{{\mathrm {ox}}}$ </tex-math></inline-formula> for the trench SiO<sub>2</sub> structure. It is observed that the total capacitance after the inclusion of Debye length is <inline-formula> <tex-math notation="LaTeX">$1.29 \times 10^{-4} {\mathrm {F/m}}^{2}$ </tex-math></inline-formula>. Furthermore, the number of ions is also calculated from the electrical characteristics, and it is almost comparable with the number of ions in the molar solution. Overall, the proposed fabricated structure, although simple, enables to accommodate any liquid as a channel and provides an easy way to develop electrolyte-based sensors.
Circuits, Systems, and Signal Processing
In the past years, several QRS complex (Q, R and S wave) detecting algorithms have been implement... more In the past years, several QRS complex (Q, R and S wave) detecting algorithms have been implemented in software, but they are not applicable for real-time operation due to their mathematical complexity. Hence, this paper focuses on developing an algorithm which enables detection of QRS complex in real time. Here, Integer Haar Wavelet Transform is employed which is used for the purpose of filtering ECG signal and detecting the R-peak frequency of QRS complex. Various blocks of the proposed architecture are implemented in a Digilent Nexys 4 double data rate field-programmable gate array board with only 501 flip-flops and 557 look-up tables utilized which makes it suitable for directly installing it into medical equipment or further developing a smart internet of things system for bio-medical applications. To make the designed system more generic, several similar blocks or components have been used. At first, the principle of using wavelet to detect QRS complex is explored theoretically and accordingly used for developing our system. An efficient hardware architecture is implemented incorporating many simplifications, a significant one being approximation of floating point arithmetic to integer arithmetic, required for wavelets. The architecture of the designed system is represented with demonstration in behavioral simulation as well as hardware testing. In the end, the system is analyzed and results are obtained with an error percentage in RR interval computation of less than 1.4% and QRS detection accuracy of 98.76%. The proposed architecture is also synthesized using 130 nm technology which produces 0.717% of leakage power. The developed architecture can be used for analysis of other bio-medical signals where the operation of wavelet transform in hardware is required.
IETE Journal of Research
Room temperature RF magnetron sputtering deposition of Zinc Oxide thin films on a glass substrate... more Room temperature RF magnetron sputtering deposition of Zinc Oxide thin films on a glass substrate was carried out by varying deposition parameters such as sputtering pressure, target-to-substrate distance, and RF power. The as-deposited film at 75 W, sputtering pressure of 9.8 mbar and a target-to-substrate distance of 104 mm has showed a band gap of 3.31 eV and RMS surface roughness of 7.1 nm. Electrical characterization and UV–VIS results reveal its high resistivity (1.3 × 107 Ω-cm) and transparency >86% in a wide optical range (494–1100 nm). This film could be used as a buffer layer of CIS solar cells, SAW, and other similar thin film devices over a flexible substrate.
Journal of Electronic Materials
This work deploys the density functional theory to study the interactions between urea with prist... more This work deploys the density functional theory to study the interactions between urea with pristine and transition metal (TM)-doped two-dimensional (2D) graphene structures. Four TM dopants, namely, V, Ti, Fe, and Cr, are considered in this study. Each of these doped structures has one TM atom replacing one carbon atom from 2D graphene sheets. Our results indicate that TM-doped graphene possesses strong chemical interactions with the urea molecule and, hence, has a better affinity towards urea as compared to pristine 2D graphene sheet. Significant charge transfer has also been observed between TM and O atoms. Moreover, among all the TM-doped structures, the V-doped structure is preferred in terms of adsorption energy. The electronic structure also changes after adsorption, which can be observed through the change in the density of states. Our study suggests that TM-doped graphene has the potential to be a sensing platform for urea.
IEEE Transactions on Electron Devices
Transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, MoTe2, WS2, WSe2, etc., have been c... more Transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, MoTe2, WS2, WSe2, etc., have been considered as the most promising candidates for energy-efficient information processing at ultrascaled devices due to their decent energy gap of around 1–2 eV and single-atomic thickness. Even though there are many efforts to explore their performance for digital applications, their performance considerations for analog/mixed-signal applications are still unexplored. In this regard, we have assessed the analog/RF performance of TMD-based field-effect transistors (TMD-FETs) and investigated their benefits over graphene-FET and black phosphorous-FETs. The performance analysis is done by an in-house developed code, which involves the self-consistent solutions of 2-D Poisson’s equation and nonequilibrium Green’s function (NEGF) formalism. The results show that MoS2-FET can offer high intrinsic gain with the intrinsic cutoff frequency and maximum oscillation frequency in terahertz range. However, the significant degradation in high-frequency performance of MoS2-FET is observed in the presence of external resistances and parasitic capacitances. The cutoff frequency has found a few hundreds of gigahertz range in the presence of all parasitic conditions. It has also found that, among TMD-FETs, WSe2-FET could be a promising candidate for analog/RF integrated circuits with a higher drive current, intrinsic gain, cutoff frequency, and maximum oscillation frequency.
IEEE Transactions on Industrial Informatics
This paper presents the design and implementation of ultrawideband digital baseband transceiver f... more This paper presents the design and implementation of ultrawideband digital baseband transceiver for wireless body area networks (WBAN) applications. The power dissipation and area of the proposed architecture are minimized by combining algorithmic and architectural level modifications. A new algorithm for Bose–Chaudhuri–Hocquenghem (BCH) encoding is implemented and the coding gain of the BCH decoder is improved by 0.5 dB, with a cost of only one percent area overhead. An area efficient, low-complexity, and low-power BCH decoder is implemented and it has 42<inline-formula><tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> lower area and 38<inline-formula><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> lower power dissipation compared to a conventional hard-decision decoder. Other salient features of this paper include a low-complexity, low-power packet detection unit, and a low-power module for removing the shortening bits. The baseband transceiver has been designed in 90 nm CMOS technology and it has an energy efficiency of 73 pJ/bit in transmitter mode and 225 pJ/bit in receiver mode.
IEEE Internet of Things Journal
Extracting maximum power from a photovoltaic (PV) harvester with minimum power transfer loss is o... more Extracting maximum power from a photovoltaic (PV) harvester with minimum power transfer loss is one of the primary design goals of an energy processing circuit. This paper presents a fully integrated PV power harvesting system with a low-overhead adaptive maximum power point tracking (MPPT) scheme for Internet-of-Things (IoT) nodes. The proposed scheme tracks the MPPs within 12 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> by utilizing an inherent negative feedback loop, within a tracking error of 0.6%. The tracking range has been improved by ~57% using a current-starved voltage-controlled oscillator (CS-VCO) instead of a polynomial VCO. The overhead area and power consumed by this tracking scheme are approximately 0.013% and 0.1%, respectively. Using commercially available solar cell of area 11.3 cm<sup>2</sup>, the proposed system can provide 833 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> of power with a light intensity of 600 lx. The proposed energy processing circuit has been designed using 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology node and the circuit simulations demonstrate that the proposed scheme can track maximum power point (MPP) under rapidly changing atmospheric conditions with a peak tracking efficiency of 99%.
2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 2016
The main objective of this paper aims at designing an efficient blind assistance system for the v... more The main objective of this paper aims at designing an efficient blind assistance system for the visually impaired people using real time disparity estimation algorithm. The local window based matching algorithms known as sum of absolute differences (SAD) and zero-mean SAD (ZSAD) are used for the disparity estimation and efficient hardware architectures for those algorithms are implemented in FPGA. The SAD and ZSAD algorithms are implemented for the image resolution of 640x360 pixels with square window of size 8x8 pixels and with a disparity range of 0 to 99. An efficient line buffering scheme for the left and right window of the two camera images is implemented to support the parallel processing mechanism. To provide high frame rate per second (fps) to the artificial vision system, parallel processing architecture for disparity estimation is required, but it consumes huge amount of hardware resources which is not desirable for this application. So, semi-parallel architectures are implemented for SAD and ZSAD algorithms for a compromise between hardware resource utilization and speed. The FPGA resource utilization for the ZSAD and SAD algorithms for a frame rate of 30 fps are 43529 LUTs, 50144 FFs and 34548 LUTs, 37544 FFs respectively. ZSAD algorithm consumes around 30% more hardware resources compared to SAD, but to counter the randomized distortion caused by the non-ideal stereo cameras ZSAD is more preferred. Finally from the disparity, the distance of the nearest obstacle is estimated and blind person is alerted through audio device instructions.
2017 Devices for Integrated Circuit (DevIC)
In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on... more In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on the backbone of polymers of thiophene, selenophene and tellurophene and their hexyl derivatives by studying the effect on their molecular orbital structure at the B3LYP/6-31G level of theory. The effects on photovoltaic properties are also estimated using the well-established Scharber model to predict change in open-circuit voltage Voc when compared with P3HT which is a benchmark for such polymers. Fluorination was seen to increase predicted Voc in all cases whereas the Se and Te heteroatoms afforded a lower bandgap towards higher values of short-circuit current Jsc.
TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON)
In this paper, we present a new 10T design for static random access memory (SRAM). The proposed d... more In this paper, we present a new 10T design for static random access memory (SRAM). The proposed design simultaneously aims to address stability, power and half select issues. The design metrics such as power, delay, and stability of the proposed design are compared with 7T, 11T, and 9T SRAM cells. It is observed that the proposed design reduces read and write power by 27.69% and 41.72% as compared to 11T and 9T SRAM cell. Furthermore, WSNM of the proposed SRAM is larger as compared to 7T, 9T and 11T. In addition, the RSNM is larger than 7T and 9T. The simulation result confirms that the proposed design is effective for low power application.
Oxide reliability is a major concern for the thin gate oxides of future ULSI technology. For cont... more Oxide reliability is a major concern for the thin gate oxides of future ULSI technology. For controlled growth of ultra-thin oxide, it is necessary to carry out the gate oxidation at comparatively lower temperature. However, due to the increase of the weak spots and pinholes in the low temperature grown oxides, they exhibit poor dielectric strength, high leakage current and high interface trap densities. This paper proposes a method, which identifies the weak spots and repairs them by selective anodisation. After the thermal gate oxidation, during the anodisation, current flows only through the weak spots in the oxide. Anodic oxide therefore grows over these weak spots, improving the stability of the oxide. An improvement in electrical characteristics was observed in the gate oxides treated by anodic oxidation under optimized conditions.
IEEE Transactions on Circuits and Systems II: Express Briefs
Design of high-performance processors with very low power requirement is the primary goal of many... more Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm<sup>2</sup> area and <inline-formula> <tex-math notation="LaTeX">$17.36~\mu \text{W}$ </tex-math></inline-formula>/MHz power requirement at UMC 40 nm technology node. The core consumes a dynamic power of <inline-formula> <tex-math notation="LaTeX">$19.75~\mu \text{W}$ </tex-math></inline-formula>/MHz at UMC 90nm which is 36% and 40% better than ARM Cortex-M3 and Cortex-M4 respectively and also lower than many others cores. The results show that this core can outperform many existing commercial and open-source cores.
2017 Devices for Integrated Circuit (DevIC), 2017
In this work, we employed Density Functional Theory (DFT), to study the interactions between NO a... more In this work, we employed Density Functional Theory (DFT), to study the interactions between NO and CO with Ti-doped zigzag graphene nanoribbon (ZGNR) structures. Two types of doped structures are considered i.e. SV-ZGNR in which Ti replaces one carbon atom and DV-ZGNR replacing two adjacent carbon atoms. Our results indicate that doped ZGNR is better for gas adsorption as compared to already reported doped 2-D graphene sheet. Also between the two doped structures, DV-ZGNR is preferred over SV-ZGNR in terms of adsorption. The changes in the electronic structures after the adsorption can be seen in terms of changes in the Density of states. Our study suggests that Ti-doped ZGNR can have the potential to be the sensing platform for these gases.
In this paper, we discuss a simplified finite element method (FEM) simulation of surface acoustic... more In this paper, we discuss a simplified finite element method (FEM) simulation of surface acoustic wave (SAW) delay line hydrogen sensor using COMSOL Multiphysics. A delay line SAW sensor consists of a transmitting interdigital transducer (IDT) and a receiving IDT separated by a few wavelengths. In this paper, the number of degrees of freedom (DOF) to solve for the SAW delay line sensor model is minimized by providing periodic boundary conditions to the transmitting IDT, which is a one finger structure. Further a palladium thin film is coated over the delay line. The palladium film transforms to palladium hydride in the presence of hydrogen. This change in palladium properties are provided to the assumed thin film over the delay line. The time domain analysis of SAW sensor with and without the presence of hydrogen is performed and change in velocity of the SAW is observed.
In this work, design of Fractional-N Frequency Synthesizer using PLL has been investigated. The s... more In this work, design of Fractional-N Frequency Synthesizer using PLL has been investigated. The simulation is done in 0.18 μm CMOS technology with CADENCE tools using UMC foundry models. The different parts of synthesizer discussed in detail. Three different phase detector architectures are implemented. High speed TSPC DFF has designed to divide the frequency of GHz range. The prescalar is modified to have a delay of 80 ps only. For VCO, a multi layer inductor is used to save the area. The phase noise can be further reduced with a ΔΣ modulator in feedback loop. The designed frequency synthesizer targets RF applications like DVB-SH, WLAN, 802.11, bluetooth, cordless phones and remote control. Keyword: VCO, TSPC DFF, phase detector.
In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on... more In this work, we employ density functional theory (DFT) to analyze the effects of fluorination on the backbone of polymers of thiophene, selenophene and tellurophene and their hexyl derivatives by studying the effect on their molecular orbital structure at the B3LYP/6-31G level of theory. The effects on photovoltaic properties are also estimated using the well-established Scharber model to predict change in open-circuit voltage Voc when compared with P3HT which is a benchmark for such polymers. Fluorination was seen to increase predicted Voc in all cases whereas the Se and Te heteroatoms afforded a lower bandgap towards higher values of short-circuit current Jsc.
Design of high-performance processors with very low power requirement is the primary goal of many... more Design of high-performance processors with very low power requirement is the primary goal of many contemporary and futuristic applications. This brief presents a novel processor micro-architecture which is capable of achieving these requirements. The micro-architecture is based on RISC-V Instruction Set Architecture (ISA). The core is implemented and verified on Xilinx Virtex-7 FPGA board with a resource requirement of 7617 LUTs and 2319 FFs. This core could achieve a Dhrystone benchmark score of 1.71 DMIPS per MHz which is higher than ARM Cortex-M3 (1.50 DMIPS per MHz) and ARM Cortex-M4 (1.52 DMIPS per MHz). The Coremark benchmark is also tested on this core and it gives 4.13 Coremark per MHz. The physical design result of the core using commercial tools shows that it can achieve a maximum frequency of 198.02 MHz with 0.036 mm<sup>2</sup> area and <inline-formula> <tex-math notation="LaTeX">$17.36~\mu \text{W}$ </tex-math></inline-formula&...
This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalizatio... more This paper proposes a un-grouped-sliding-window-technique (UGSWT) and a state metric normalization technique for logarithmic maximum-a-posteriori-probability (LMAPP) algorithm. We have suggested a decoder architecture based on these techniques for high throughput application. Application-specific-integrated-circuit (ASIC) implementation of the proposed decoder is carried out in 90 nm complementary-metal-oxide-semiconductor (CMOS) process and it has achieved a throughput of 612 Mbps at a maximum clock frequency of 625 MHz with an energy efficiency of 0.1 nJ/bit. Functional verification of the implemented channel decoder is carried out using field-programmable gate-array (FPGA) which is interconnected with logic analyzer via high-speed-data-transfer card. Bit-error-rate (BER) performance of the implemented decoder has shown a coding loss of approximately 0.2 dB in comparison with the simulated BER values.
IEEE Transactions on Nanotechnology
This article describes the fabrication of Zinc Ferrite-Zinc oxide (ZFO-ZnO) heterostructure devic... more This article describes the fabrication of Zinc Ferrite-Zinc oxide (ZFO-ZnO) heterostructure devices and the various sensing schemes that can be exploited using the same. A solvothermal approach has been used for the synthesis of ZFO-ZnO heterostructures having different compositions. The investigation of magnetic and electric properties is performed by varying the ratio of Zn<inline-formula><tex-math notation="LaTeX">$^{2+}$</tex-math></inline-formula> and Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ions. These heterostructures show enhanced magnetization with (i) an increase in the concentration of Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ions and (ii) exposure to hydrogen (H<inline-formula><tex-math notation="LaTeX">$_2$</tex-math></inline-formula>) gas. These fine molar ratio adjustments in magnetism are engineered to obtain desirable sensing properties. We fabricated several two-terminal devices for the study of multiple sensing schemes. These devices demonstrated a linear current-voltage characteristic, with enhanced electrical resistance when the Fe<inline-formula><tex-math notation="LaTeX">$^{3+}$</tex-math></inline-formula> ion concentration is reduced. Keywords- Magnetic analysis, Zinc Ferrite-Zinc oxide, sensors, room temperature, heterostructures, tunability and nanotechnology
Materials Horizons
Here, an extremely water-repellent, abrasion tolerant and low-strain based motions/expressions de... more Here, an extremely water-repellent, abrasion tolerant and low-strain based motions/expressions detecting pattern interface having ultra-sensitivity (∼18 300 for applied strain of 0.2%) has been introduced through strategic use of 1,4-conjugate addition reaction.
IEEE Transactions on Electron Devices
This work explores the fabrication and characterization of an ionic liquid channel field effect t... more This work explores the fabrication and characterization of an ionic liquid channel field effect transistor (FET) incorporated within the trench structure on SiO<sub>2</sub>. The trench structure allows any liquid to be accommodated, thereby eliminating the mold creation on the device or the requirement for an intricate architecture to store liquid. For the fabrication of the trench, we followed a standard photolithography process with the help of selective etching of aluminum and SiO<sub>2</sub>. The fabricated trench surface is characterized using atomic force microscopy (AFM) and contact angle analysis. The electrical characterization of the proposed FET structure is also performed with 0.01-mM potassium chloride (KCl) solution as an ionic channel. We tested both the n-FET and p-FET type characteristics which can be controlled by the back gate biasing condition. The dc characterization shows a high <inline-formula> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio of 10<sup>5</sup> for both the n-FET and p-FET. The device further shows an improvement in K<sup>+</sup> mobility and Cl<sup>−</sup> mobility of <inline-formula> <tex-math notation="LaTeX">$2.24 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$4.96 \times 10^{-4} {\mathrm {m}}^{2}/{\mathrm {Vs}}$ </tex-math></inline-formula>, respectively. We also carried out the FET structure modeling to estimate the effective <inline-formula> <tex-math notation="LaTeX">${C}_{{\mathrm {ox}}}$ </tex-math></inline-formula> for the trench SiO<sub>2</sub> structure. It is observed that the total capacitance after the inclusion of Debye length is <inline-formula> <tex-math notation="LaTeX">$1.29 \times 10^{-4} {\mathrm {F/m}}^{2}$ </tex-math></inline-formula>. Furthermore, the number of ions is also calculated from the electrical characteristics, and it is almost comparable with the number of ions in the molar solution. Overall, the proposed fabricated structure, although simple, enables to accommodate any liquid as a channel and provides an easy way to develop electrolyte-based sensors.
Circuits, Systems, and Signal Processing
In the past years, several QRS complex (Q, R and S wave) detecting algorithms have been implement... more In the past years, several QRS complex (Q, R and S wave) detecting algorithms have been implemented in software, but they are not applicable for real-time operation due to their mathematical complexity. Hence, this paper focuses on developing an algorithm which enables detection of QRS complex in real time. Here, Integer Haar Wavelet Transform is employed which is used for the purpose of filtering ECG signal and detecting the R-peak frequency of QRS complex. Various blocks of the proposed architecture are implemented in a Digilent Nexys 4 double data rate field-programmable gate array board with only 501 flip-flops and 557 look-up tables utilized which makes it suitable for directly installing it into medical equipment or further developing a smart internet of things system for bio-medical applications. To make the designed system more generic, several similar blocks or components have been used. At first, the principle of using wavelet to detect QRS complex is explored theoretically and accordingly used for developing our system. An efficient hardware architecture is implemented incorporating many simplifications, a significant one being approximation of floating point arithmetic to integer arithmetic, required for wavelets. The architecture of the designed system is represented with demonstration in behavioral simulation as well as hardware testing. In the end, the system is analyzed and results are obtained with an error percentage in RR interval computation of less than 1.4% and QRS detection accuracy of 98.76%. The proposed architecture is also synthesized using 130 nm technology which produces 0.717% of leakage power. The developed architecture can be used for analysis of other bio-medical signals where the operation of wavelet transform in hardware is required.
IETE Journal of Research
Room temperature RF magnetron sputtering deposition of Zinc Oxide thin films on a glass substrate... more Room temperature RF magnetron sputtering deposition of Zinc Oxide thin films on a glass substrate was carried out by varying deposition parameters such as sputtering pressure, target-to-substrate distance, and RF power. The as-deposited film at 75 W, sputtering pressure of 9.8 mbar and a target-to-substrate distance of 104 mm has showed a band gap of 3.31 eV and RMS surface roughness of 7.1 nm. Electrical characterization and UV–VIS results reveal its high resistivity (1.3 × 107 Ω-cm) and transparency >86% in a wide optical range (494–1100 nm). This film could be used as a buffer layer of CIS solar cells, SAW, and other similar thin film devices over a flexible substrate.
Journal of Electronic Materials
This work deploys the density functional theory to study the interactions between urea with prist... more This work deploys the density functional theory to study the interactions between urea with pristine and transition metal (TM)-doped two-dimensional (2D) graphene structures. Four TM dopants, namely, V, Ti, Fe, and Cr, are considered in this study. Each of these doped structures has one TM atom replacing one carbon atom from 2D graphene sheets. Our results indicate that TM-doped graphene possesses strong chemical interactions with the urea molecule and, hence, has a better affinity towards urea as compared to pristine 2D graphene sheet. Significant charge transfer has also been observed between TM and O atoms. Moreover, among all the TM-doped structures, the V-doped structure is preferred in terms of adsorption energy. The electronic structure also changes after adsorption, which can be observed through the change in the density of states. Our study suggests that TM-doped graphene has the potential to be a sensing platform for urea.
IEEE Transactions on Electron Devices
Transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, MoTe2, WS2, WSe2, etc., have been c... more Transition metal dichalcogenides (TMDs), such as MoS2, MoSe2, MoTe2, WS2, WSe2, etc., have been considered as the most promising candidates for energy-efficient information processing at ultrascaled devices due to their decent energy gap of around 1–2 eV and single-atomic thickness. Even though there are many efforts to explore their performance for digital applications, their performance considerations for analog/mixed-signal applications are still unexplored. In this regard, we have assessed the analog/RF performance of TMD-based field-effect transistors (TMD-FETs) and investigated their benefits over graphene-FET and black phosphorous-FETs. The performance analysis is done by an in-house developed code, which involves the self-consistent solutions of 2-D Poisson’s equation and nonequilibrium Green’s function (NEGF) formalism. The results show that MoS2-FET can offer high intrinsic gain with the intrinsic cutoff frequency and maximum oscillation frequency in terahertz range. However, the significant degradation in high-frequency performance of MoS2-FET is observed in the presence of external resistances and parasitic capacitances. The cutoff frequency has found a few hundreds of gigahertz range in the presence of all parasitic conditions. It has also found that, among TMD-FETs, WSe2-FET could be a promising candidate for analog/RF integrated circuits with a higher drive current, intrinsic gain, cutoff frequency, and maximum oscillation frequency.
IEEE Transactions on Industrial Informatics
This paper presents the design and implementation of ultrawideband digital baseband transceiver f... more This paper presents the design and implementation of ultrawideband digital baseband transceiver for wireless body area networks (WBAN) applications. The power dissipation and area of the proposed architecture are minimized by combining algorithmic and architectural level modifications. A new algorithm for Bose–Chaudhuri–Hocquenghem (BCH) encoding is implemented and the coding gain of the BCH decoder is improved by 0.5 dB, with a cost of only one percent area overhead. An area efficient, low-complexity, and low-power BCH decoder is implemented and it has 42<inline-formula><tex-math notation="LaTeX">$\%$</tex-math> </inline-formula> lower area and 38<inline-formula><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> lower power dissipation compared to a conventional hard-decision decoder. Other salient features of this paper include a low-complexity, low-power packet detection unit, and a low-power module for removing the shortening bits. The baseband transceiver has been designed in 90 nm CMOS technology and it has an energy efficiency of 73 pJ/bit in transmitter mode and 225 pJ/bit in receiver mode.
IEEE Internet of Things Journal
Extracting maximum power from a photovoltaic (PV) harvester with minimum power transfer loss is o... more Extracting maximum power from a photovoltaic (PV) harvester with minimum power transfer loss is one of the primary design goals of an energy processing circuit. This paper presents a fully integrated PV power harvesting system with a low-overhead adaptive maximum power point tracking (MPPT) scheme for Internet-of-Things (IoT) nodes. The proposed scheme tracks the MPPs within 12 <inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> by utilizing an inherent negative feedback loop, within a tracking error of 0.6%. The tracking range has been improved by ~57% using a current-starved voltage-controlled oscillator (CS-VCO) instead of a polynomial VCO. The overhead area and power consumed by this tracking scheme are approximately 0.013% and 0.1%, respectively. Using commercially available solar cell of area 11.3 cm<sup>2</sup>, the proposed system can provide 833 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> of power with a light intensity of 600 lx. The proposed energy processing circuit has been designed using 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology node and the circuit simulations demonstrate that the proposed scheme can track maximum power point (MPP) under rapidly changing atmospheric conditions with a peak tracking efficiency of 99%.