Sherif Sharroush - Academia.edu (original) (raw)

Papers by Sherif Sharroush

Port-Said Engineering Research Journal, Mar 27, 2024

Jordan journal of electrical engineering, Dec 31, 2022

Domino logic finds a wide variety of applications in both static and dynamic random-access memori... more Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.

There is no doubt that the CMOS technology scaling affects significantly the performance of the o... more There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The metrics that are taken as the criteria for evaluating the performance of the DRAM are the chip area, the power consumption, the cycle time, and the sense margin. The simulation results ascertain this impact.

International Journal of Circuit Theory and Applications, May 3, 2023

SummaryCMOS circuits usually operate either in the voltage, current, charge, or time domain. Each... more SummaryCMOS circuits usually operate either in the voltage, current, charge, or time domain. Each of these domains has its own features. As the fan‐in of CMOS circuits increases, the performance of circuits that operate in the voltage domain, the current domain, or the charge domain degrades. This is the case especially with scaling down the power‐supply voltage associated with technology scaling. In this paper, a time‐mode scheme that utilizes a floating‐gate MOSFET (FGMOS) transistor is proposed. The proposed scheme showed good performance for wide fan‐in NAND and NOR gates. The design issues of the proposed scheme like the speed and the power consumption are investigated quantitatively. The performance of the proposed scheme is confirmed through simulation using the 45‐nm CMOS predictive technology model (PTM) with a 1‐V power‐supply voltage. 64‐input NAND and NOR gates realized using this scheme have time delays of 0.375 and 0.25 ns, respectively, at a load capacitance of 5 fF. The application of the proposed scheme for realizing multiplexers required in register files is illustrated and compared with the conventional domino logic in the superthreshold, near‐threshold, and subthreshold regions.

e & i Elektrotechnik und Informationstechnik, 2012

ABSTRACT Während des Leseprozesses von dynamischen Ein-Transistor-/Ein-Kondensator-DRAM-Speicherz... more ABSTRACT Während des Leseprozesses von dynamischen Ein-Transistor-/Ein-Kondensator-DRAM-Speicherzellen (1T-1C DRAM) ist es notwendig, eine kleine Spannungsdifferenz (im Bereich von 30 mV bis 100 mV) mit einem entsprechenden Leseverstärker zu verstärken. Daraus resultierend wächst die höhere Spannung zu V DD an, während die niedrigere Spannung auf 0 V sinkt. Die Simulationsergebnisse für die 0,13 μm CMOS-Technologie mit VDD = 1,2 V zeigen, dass ungefähr 40 % der Lesezugriffszeit dem Leseverstärker zugeordnet werden kann – zusätzlich zur benötigten Siliziumfläche der Leseverstärker für jede Spalte im Speicherbereich. In der vorliegenden Arbeit wird eine neuartige Auslesetechnik für die Verwendung von DRAM-Zellen präsentiert. Diese Methode basiert auf einer anfänglich geladenen Kapazität und der dann folgenden Entscheidung, ob sie entsprechend der gespeicherten Daten geladen bleiben oder wieder entladen werden soll. Die Simulationsergebnisse zeigen, dass ungefähr 20 % der Lesezugriffszeit im Fall einer "1"-Speicherung, die den schlechtesten Fall darstellt, eingespart werden können. Die durchschnittliche Leistung der konventionellen Regelung im Fall einer "1"- oder "0"-Speicherung beträgt 18,5 μW. Die entsprechenden Werte für die vorgeschlagene Regelung lauten 9,8 μW und 2,25 μW. Die signifikante Verringerung des Stromverbrauchs kann der Reduzierung des Spannungshubs an der Bitline-Kapazität und der Tatsache, dass die Ausgabedaten an einer wesentlich geringeren Kapazität abgegriffen werden, zugeschrieben werden. Das Leistungsverzögerungsprodukt (PDP) beträgt – ausgehend vom schlechtest möglichen Fall (Speicherung "1") – für das konventionelle bzw. vorgeschlagene Ausleseverfahren 388,5 fJ bzw. 166,6 fJ.

Jordan Journal of Electrical Engineering

— In this paper, an electronically tunable universal biquadratic voltage-mode filter that is base... more — In this paper, an electronically tunable universal biquadratic voltage-mode filter that is based only on MOS transistors is proposed. Configuration of the proposed filter is simple and there is no need to use component matching. Since the proposed filter contains only MOS transistors, it is very suitable for implementation in system-on-chip (SoC) applications. The cutoff frequency of the lowpass (LP) and highpass (HP) filters as well as the center frequency and the bandwidth of the bandpass (BP) and bandstop (BS) filters can be controlled either in a continuous range or in a discrete manner by means of a digital control word. Besides, the filter type can be changed during the real time by an appropriate code. Operation of all the filtering functions are verified by simulation using the Berkeley predictive-technology models (BPTM) of the 130 nm complementary metal-oxide semiconductor (CMOS) technology with power-supply voltage, VDD, of 1.2 V. The proposed filter is analyzed quantitatively, and the effects of the total-harmonic distortion (THD), noise, process, voltage and temperature (PVT) variations are also investigated. The average power consumption of the LP, HP, BP, BS, and allpass (AP) filters are found to be 30, 118, 74, 118, and 30 (all in µW). The price paid for all these advantages is more sensitivity to process variations for the lowpass filter.

Ain Shams Engineering Journal

2018 International Japan-Africa Conference on Electronics, Communications and Computations (JAC-ECC), 2018

In this paper, a novel variable-gain amplifier (VGA) and a novel voltage-controlled ring oscillat... more In this paper, a novel variable-gain amplifier (VGA) and a novel voltage-controlled ring oscillator (VCRO) are proposed. The two proposed schemes depend on the same controlled inverter unit with a single added device. The relationship between the voltage gain of the proposed VGA and the control voltage and the relationship between the oscillation frequency of the proposed VCRO and the control voltage are both derived. Finally, the proposed VGA and VCRO are simulated adopting the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V.

2016 5th International Conference on Electronic Devices, Systems and Applications (ICEDSA), 2016

There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing... more There is no doubt that static CMOS circuits are the best candidate for low-power and high-packing density applications. However, its performance degrades with increasing the fan-in. In this paper, a novel fast CMOS circuit that is based on a current race is presented and compared with the conventional CMOS logic from the points of view of area, power consumption, and average-time delay. The scheme is verified by simulation adopting the 45 nm CMOS technology with Vdd = 1 V and a 25% reduction in the average propagation delay for a six-input NAND gate is achieved.

Port-Said Engineering Research Journal

2019 7th International Japan-Africa Conference on Electronics, Communications, and Computations, (JAC-ECC), 2019

During the readout of the one-transistor one-capacitor dynamic-random-access memories (1T-1C DRAM... more During the readout of the one-transistor one-capacitor dynamic-random-access memories (1T-1C DRAMs), the need arises to deal with the relatively large parasitic capacitance of the bitline. In this paper, a novel fast readout scheme is proposed that depends on charge sharing between the bitline-parasitic capacitance and another properly sized capacitor. The 45 nm CMOS Berkeley predictive-technology model (BPTM) is used in verifying the proposed readout scheme. According to the simulation results, approximately 25% of the average read-access time is saved.

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

The MOS current-mode logic (MCML) family is suitable for high-frequency applications due to the u... more The MOS current-mode logic (MCML) family is suitable for high-frequency applications due to the use of a static current source, thus relatively stabilizing its power consumption. However, there are various tradeoffs in the design of this family due to the contradictions that arise when choosing values for the load resistance or the current-source strength. In this paper, the performance of the MCML family will be investigated by using a figure of merit. The performance metrics will be derived in terms of the design parameters and the values of these parameters that correspond to the optimum performance will be estimated (if found). The analysis will be verified by comparison with the simulation results adopting the 45 nm CMOS technology.

2016 5th International Conference on Electronic Devices, Systems and Applications (ICEDSA), 2016

During the analysis of circuits containing multi transistors, the researcher is faced with a trem... more During the analysis of circuits containing multi transistors, the researcher is faced with a tremendous problem. This is due to the fact the MOS/BJT transistor is a four/three-terminal device with a large number of specifying parameters. In order to simplify the analysis, the four/three-terminal complicated MOS/BJT transistor can be replaced by a two-terminal fictitious resistor with a proper resistance. In this paper, a procedure is described to find a formula for the equivalent resistance of the MOS or the BJT transistor, and thus simplifying the analysis of such circuits considerably. Also, the procedure is applied to circuits containing a single transistor and to circuits containing series and parallel connections of transistors in order to estimate the propagation delays. The derived formulas are verified by comparison with the simulation results adopting the 65 nm CMOS technology with a power-supply voltage of 1 V.

2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2015

Reading one-transistor one capacitor ferroelectric random-access memory (1T-1C FRAM) requires gen... more Reading one-transistor one capacitor ferroelectric random-access memory (1T-1C FRAM) requires generating a reference voltage that is ideally halfway between the two bitline voltages generated in cases of "1" and "0" readings. However, these two generated voltages vary from cell to cell and with the process variations. So, a self-referenced scheme is needed. In this paper, a self-referenced readout scheme will be proposed that depends on properly pulsing the plateline and using a capacitive-voltage divider. The proposed scheme is verified using simulation adopting the 45 nm CMOS technology and shows a 33% reduction in the read-cycle time. Enhancing the robustness of the reading circuitry will also be investigated quantitatively.

2016 5th International Conference on Electronic Devices, Systems and Applications (ICEDSA), 2016

In radio-frequency receivers, variable-gain amplifiers (VGAs) are often used in order to compensa... more In radio-frequency receivers, variable-gain amplifiers (VGAs) are often used in order to compensate for the change of the signal level during the channel transmission and to relax the constraints on the succeeding analog-to-digital converter (ADC). In this paper, a novel VGA is introduced using a floating-gate MOS transistor (FGMOS). The voltage gain, the linearity, the valid region for proper operation, and the sensitivity are discussed and quantitative expressions are derived for them. The performance of this amplifier is verified by simulation adopting the 45 nm CMOS technology with Vdd = 1 V.

2016 International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT), 2016

2019 31st International Conference on Microelectronics (ICM), 2019

The one-transistor one-capacitor (1T −1C) memory cell is considered the industry standard in dyna... more The one-transistor one-capacitor (1T −1C) memory cell is considered the industry standard in dynamic random-access memories (DRAMs) due to its low cost and high packing density. The main challenge associated with this type of memories is the relatively large read-access time due to the need to deal with the relatively large parasitic capacitance of the bitline. In this paper, a novel fast readout scheme is proposed in the current domain. The proposed scheme is verified by simulation adopting the 45 nm CMOS Berkeley predictive-technology model (BPTM). The average read-access time is 30% smaller than that of the conventional readout.

Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant... more Wide fan-in logic gates when implemented in static complementary CMOS logic consume a significant area overhead, consume a large power consumption, and have a large propagation delay. In this paper, a pseudo-PMOS logic is presented for the realization of wide fan-in NAND gates in a manner similar to the realization of wide fan-in NOR gates using the pseudo-NMOS logic. The circuit design issues of this family are discussed. Also, it is compared with the conventional CMOS logic from the points of view of the area, the average propagation delay, the average power consumption, and the logic swing using a proper figure of merit. The effects of technology scaling and process variations on this family are investigated. Simulation results verify the enhancement in performance in which the 45 nm CMOS technology is adopted.

Mathematical and Computer Modelling of Dynamical Systems, 2021

During the analysis of multi-transistor circuits, the need arises to evaluate the time delay or t... more During the analysis of multi-transistor circuits, the need arises to evaluate the time delay or the power consumption of the circuit. Due to the complexity of the transistor model, several complica...