Krishna Santhanam - Academia.edu (original) (raw)
Uploads
Papers by Krishna Santhanam
Dynamic logic can provide significant performance and power benefit compared to implementations u... more Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.
Static circuit gates are the standard circuit devices used to build the major parts of digital ci... more Static circuit gates are the standard circuit devices used to build the major parts of digital circuits. Dynamic gates, such as domino circuits, are only used in certain sections of the circuit where speed is critical. These gates achieve higher speed compared to static gates at the cost of reduced noise margins. We propose a novel gate structure that tries to improved noise margin when compared to dynamic domino gates with a standard keeper while retaining some advantage over static gates in terms of performance and switching energy. Here we make a comparison between static, dynamic domino, dynamic domino with noise tolerant precharge and our novel domino static gates in terms of noise, switching energy and transition delay. Motivation Dynamic domino gates are able to achieve lower delays and less switching energy when compared to static gates because of their ability to source substantially more output current for the same input load capacitance. This is because, by design, the le...
2007 IFIP International Conference on Very Large Scale Integration, 2007
Dynamic logic can provide significant performance and power benefit compared to implementations u... more Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.
Dynamic logic can provide significant performance and power benefit compared to implementations u... more Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.
Static circuit gates are the standard circuit devices used to build the major parts of digital ci... more Static circuit gates are the standard circuit devices used to build the major parts of digital circuits. Dynamic gates, such as domino circuits, are only used in certain sections of the circuit where speed is critical. These gates achieve higher speed compared to static gates at the cost of reduced noise margins. We propose a novel gate structure that tries to improved noise margin when compared to dynamic domino gates with a standard keeper while retaining some advantage over static gates in terms of performance and switching energy. Here we make a comparison between static, dynamic domino, dynamic domino with noise tolerant precharge and our novel domino static gates in terms of noise, switching energy and transition delay. Motivation Dynamic domino gates are able to achieve lower delays and less switching energy when compared to static gates because of their ability to source substantially more output current for the same input load capacitance. This is because, by design, the le...
2007 IFIP International Conference on Very Large Scale Integration, 2007
Dynamic logic can provide significant performance and power benefit compared to implementations u... more Dynamic logic can provide significant performance and power benefit compared to implementations using static gates. Unfortunately dynamic gates have traditionally suffered from low noise margins, which limits their reliability. A new logic family, called complementary dynamic logic (CDL), is presented. CDL replaces the standard keeper logic with a dual dynamic keeper gate that is applicable to all dynamic gate structures. CDL provides dynamic gates with two novel characteristics: hysteresis and arbitrarily configurable noise margins. However, these two benefits come at the cost of reducing the gain and increasing the energy of the dynamic gate. This paper compares the noise, energy, performance, gain, and total transistor width tradeoffs of CDL and three other logic families applied to a 65nm cell library consisting of 23 functions. The results show that the performance advantages of dynamic domino gates can be maintained while providing significantly enhanced noise margins using CDL structures.