Srikanth Samavedam - Academia.edu (original) (raw)
Papers by Srikanth Samavedam
2017 IEEE International Electron Devices Meeting (IEDM), 2017
Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This ... more Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is used to understand the impact of gate length (Lg)scaling along with fin width scaling to optimize AC performance. In this paper, W was scaled from 8nm to 1.6nm. It was found that there is a critical fin width (Wc)at ∼4nm. In the W>Wc region, due to better electrostatics from narrower fin, drain-induced barrier lowering (DIBL), DC performance and SRAM Vt mismatch (Vtmm) were improved. As W was scaled down further to W<Wc region, DIBL benefit was reduced and DC performance degraded rapidly from drivability loss. Additionally, Vtmm improvement saturated from increased sensitivity to fin bottom punch-through. As W is reduced, TCAD simulations show reduced inversion carrier density from quantum confinement, and mobility degradation from stress relaxation (PFETs) or phonon scattering and surface roughness scattering (both NFETs and PFETs). From TCAD simulations DIBL is much less sensitive to gate length scaling for narrower fins, which can be leveraged to improve Ceff and AC performance by Lg reduction. A 16% improvement in AC performance is predicted when Lg is reduced by 6nm for FinFETs as W is scaled from 8nm to Wc∼ 4nm.
MRS Proceedings, 1998
Due to the prohibitively high 4.1% lattice mismatch, direct growth of GaAs on Si invariably leads... more Due to the prohibitively high 4.1% lattice mismatch, direct growth of GaAs on Si invariably leads to very high dislocation densities (> 10 8 /cm 2) which have precluded its use in device applications despite numerous attempts. However, the growth of low threading dislocation density (~ 2 x 10 6 /cm 2) relaxed graded Ge/Ge x Si 1-x /Si heterostructures can bridge the gap between lattice constants by replacing the high mismatch GaAs/Si interface with a low mismatch (< 0.1%) GaAs/Ge interface. Although the lattice mismatch problem is thus eliminated, the heterovalent GaAs/Ge interface remains highly susceptible to antiphase disorder. Since antiphase boundaries (APBs) nucleated at the GaAs/Ge interface act as scattering and non-radiative recombination centers, growth of device quality GaAs on Ge/Ge x Si 1-x /Si demands effective suppression of antiphase disorder. The current work investigates the sublattice location of GaAs on 6° offcut (001) Ge/Ge x Si 1-x /Si substrates as a function of atmospheric pressure metal-organic chemical vapor deposition (MOCVD) growth initiation parameters. Two distinct GaAs phases are observed, one dominant at temperatures > 600 °C and another at temperatures < 500 °C. Incomplete phase transitions during pre-growth thermal cycling account for the appearance of localized bands of antiphase disorder where the polarity of the GaAs film switches. We suspect that background arsenic levels in the MOCVD system are largely responsible for inducing the observed phase transitions. The complete suppression of antiphase disorder under optimized growth conditions is demonstrated by transmission electron microscopy (TEM).
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 1998
The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded Si1−xGex/Si buffer l... more The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded Si1−xGex/Si buffer layer would allow monolithic integration of GaAs-based opto-electronics with Si microelectronics. As an initial step toward this goal, this study examines factors which influence the quality of GaAs growth by molecular beam epitaxy (MBE) on bulk Ge substrates. Key findings include the need for an epitaxial Ge smoothing cap deposited in the MBE chamber, the significant detrimental effect of As overpressure on the resultant GaAs crystalline quality, and the efficiency of a very thin (∼3 nm) migration enhanced epitaxy (MEE) nucleation layer at suppressing both anti-phase domain (APD) formation and interdiffusion across the GaAs/Ge heterointerface. Using this developed optimized growth process, APD-free GaAs on Ge is obtained which has undetectable Ga and Ge cross-diffusion, and As diffusion into the substrate at ⩽1×1018 cm−3. Preliminary results for growths on Ge/Si1−xGex/Si substrates are a...
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 1997
Under typical growth conditions, strain levels greater than or equal to 10−4 are shown to influen... more Under typical growth conditions, strain levels greater than or equal to 10−4 are shown to influence thin film surface morphology and strain relaxation pathways. Misfit and threading dislocations in relaxed heterostructures produce long wavelength undulations on the surface and shallow depressions, respectively. Threading dislocation densities greater than ∼105–106 cm−2 in relaxed heterostructures must be due to increased impediments to dislocation motion, which in turn originate from the effect of the misfit dislocations on the surface morphology. Under typical growth conditions, the origin of strain-induced surface features can be identified by recognizing the length scale at which the features occur.
MRS Proceedings, 1997
Germanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz freque... more Germanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1-1.6 µm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pileups. The generation of pileups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pileups , decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 x 10 6 /cm 2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.
2008 IEEE International Electron Devices Meeting, 2008
This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gat... more This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gate process, down to 0.149μm 2 and 0.124μm 2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124μm 2 cell to meet low power application requirements.
2017 IEEE International Electron Devices Meeting (IEDM), 2017
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, S... more We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2006 European Solid-State Device Research Conference, 2006
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size ... more This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/mum and VDD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.
MRS Proceedings, 2002
ABSTRACTIn this paper, we report the leakage current characterization of HfO2 high-k dielectric t... more ABSTRACTIn this paper, we report the leakage current characterization of HfO2 high-k dielectric thin films by using tunneling AFM, which utilizes a conducting AFM probe to detect current passing through the sample and the probe while simultaneously acquiring a topographic image. We have studied tunneling current behavior of HfO2 films by characterizing the hot spots, which are characterized by excessive local leakage current, as well as the overall current distribution. Tunneling AFM results show sensitive dependence of tunneling current with variation of film thickness. The current distribution can be described approximately by a log-normal distribution, which is consistent with the characteristics of the thickness variation. Furthermore, the film structure and thickness were also characterized with TEM and spectroscopic ellipsometry.
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017
14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Ac... more 14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Access Distuib Margin (ADM) response to Local Layout Effect (LLE) as seen in planar CMOS technology using RMG [1]. Additionally, 14nm FinFET technology has more LLEs than ever due to the layout variety or tighter minimum design rule applied [2]. Fluorine with very high reaction energy diffuses from WL CONT to Pass Gate (PG) is found to lower PG Vtsat degrading ß-ratio and ADM. And, the STI stress from strap cell reduces the SRAM NFET Vtsat of the cell at the array edge degrading ADM. The natural variation of Gate-cut to PG degrades the Vth mismatch resulting in ADM degradation also. These three kinds of LLE and their impacts on ADM are discussed and analyzed in detail in this paper along with mechanisms that can cause the LLEs.
2020 IEEE International Electron Devices Meeting (IEDM), 2020
With each new node, cost and complexity of logic technology increases while being challenged to p... more With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (Lg) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.
IEEE Transactions on Nuclear Science, 2017
Total ionizing dose results are provided, showing the effects of different threshold adjust impla... more Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiationinduced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-V th transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V th , while the low-V th transistors exhibit a larger change in offstate leakage current. The "worst-case" bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (V gs = V dd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-V th transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)
Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-8... more Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-80-nm PD and FD SOI device performance. The optimal gate workfunction for the 50 nm technology node is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS). Midgap gates are not suitable for PD SOI CMOS due to the severe short-channel
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517), 2001
MOSFETs with a zirconium dioxide (ZrO2) gate dielectric and poly-silicon gate were fabricated usi... more MOSFETs with a zirconium dioxide (ZrO2) gate dielectric and poly-silicon gate were fabricated using a low temperature CMOS process. Well-behaved transistor characteristics were obtained for devices with sizes of 14 μm×1.4 μm or smaller. Devices 14 μm×14 μm or larger were found to be nonfunctional due to the formation of Zr-silicide at the polySi-gate/Zr02 interface. In this paper, we present
2006 IEEE International Reliability Physics Symposium Proceedings, 2006
A generalized reliability model of BTI is presented where it is shown that gate stacks with simil... more A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI
2017 IEEE International Electron Devices Meeting (IEDM), 2017
Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This ... more Fin width scaling is required to improve FinFET electrostatics for future technology nodes. This paper studies the benefits, trade-offs and limitations of aggressive fin width (W) scaling on logic and SRAM device characteristics. TCAD analysis is used to understand the impact of gate length (Lg)scaling along with fin width scaling to optimize AC performance. In this paper, W was scaled from 8nm to 1.6nm. It was found that there is a critical fin width (Wc)at ∼4nm. In the W>Wc region, due to better electrostatics from narrower fin, drain-induced barrier lowering (DIBL), DC performance and SRAM Vt mismatch (Vtmm) were improved. As W was scaled down further to W<Wc region, DIBL benefit was reduced and DC performance degraded rapidly from drivability loss. Additionally, Vtmm improvement saturated from increased sensitivity to fin bottom punch-through. As W is reduced, TCAD simulations show reduced inversion carrier density from quantum confinement, and mobility degradation from stress relaxation (PFETs) or phonon scattering and surface roughness scattering (both NFETs and PFETs). From TCAD simulations DIBL is much less sensitive to gate length scaling for narrower fins, which can be leveraged to improve Ceff and AC performance by Lg reduction. A 16% improvement in AC performance is predicted when Lg is reduced by 6nm for FinFETs as W is scaled from 8nm to Wc∼ 4nm.
MRS Proceedings, 1998
Due to the prohibitively high 4.1% lattice mismatch, direct growth of GaAs on Si invariably leads... more Due to the prohibitively high 4.1% lattice mismatch, direct growth of GaAs on Si invariably leads to very high dislocation densities (> 10 8 /cm 2) which have precluded its use in device applications despite numerous attempts. However, the growth of low threading dislocation density (~ 2 x 10 6 /cm 2) relaxed graded Ge/Ge x Si 1-x /Si heterostructures can bridge the gap between lattice constants by replacing the high mismatch GaAs/Si interface with a low mismatch (< 0.1%) GaAs/Ge interface. Although the lattice mismatch problem is thus eliminated, the heterovalent GaAs/Ge interface remains highly susceptible to antiphase disorder. Since antiphase boundaries (APBs) nucleated at the GaAs/Ge interface act as scattering and non-radiative recombination centers, growth of device quality GaAs on Ge/Ge x Si 1-x /Si demands effective suppression of antiphase disorder. The current work investigates the sublattice location of GaAs on 6° offcut (001) Ge/Ge x Si 1-x /Si substrates as a function of atmospheric pressure metal-organic chemical vapor deposition (MOCVD) growth initiation parameters. Two distinct GaAs phases are observed, one dominant at temperatures > 600 °C and another at temperatures < 500 °C. Incomplete phase transitions during pre-growth thermal cycling account for the appearance of localized bands of antiphase disorder where the polarity of the GaAs film switches. We suspect that background arsenic levels in the MOCVD system are largely responsible for inducing the observed phase transitions. The complete suppression of antiphase disorder under optimized growth conditions is demonstrated by transmission electron microscopy (TEM).
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena, 1998
The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded Si1−xGex/Si buffer l... more The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded Si1−xGex/Si buffer layer would allow monolithic integration of GaAs-based opto-electronics with Si microelectronics. As an initial step toward this goal, this study examines factors which influence the quality of GaAs growth by molecular beam epitaxy (MBE) on bulk Ge substrates. Key findings include the need for an epitaxial Ge smoothing cap deposited in the MBE chamber, the significant detrimental effect of As overpressure on the resultant GaAs crystalline quality, and the efficiency of a very thin (∼3 nm) migration enhanced epitaxy (MEE) nucleation layer at suppressing both anti-phase domain (APD) formation and interdiffusion across the GaAs/Ge heterointerface. Using this developed optimized growth process, APD-free GaAs on Ge is obtained which has undetectable Ga and Ge cross-diffusion, and As diffusion into the substrate at ⩽1×1018 cm−3. Preliminary results for growths on Ge/Si1−xGex/Si substrates are a...
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, 1997
Under typical growth conditions, strain levels greater than or equal to 10−4 are shown to influen... more Under typical growth conditions, strain levels greater than or equal to 10−4 are shown to influence thin film surface morphology and strain relaxation pathways. Misfit and threading dislocations in relaxed heterostructures produce long wavelength undulations on the surface and shallow depressions, respectively. Threading dislocation densities greater than ∼105–106 cm−2 in relaxed heterostructures must be due to increased impediments to dislocation motion, which in turn originate from the effect of the misfit dislocations on the surface morphology. Under typical growth conditions, the origin of strain-induced surface features can be identified by recognizing the length scale at which the features occur.
MRS Proceedings, 1997
Germanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz freque... more Germanium (Ge) photodiodes are capable of high quantum yields and can operate at gigahertz frequencies in the 1-1.6 µm wavelength regime. The compatibility of SiGe alloys with Si substrates makes Ge a natural choice for photodetectors in Si-based optoelectronics applications. The large lattice mismatch (≈4%) between Si and Ge, however, leads to the formation of a high density of misfit and associated threading dislocations when uniform Ge layers are grown on Si substrates. High quality Ge layers were grown on relaxed graded SiGe/Si layers by ultra-high vacuum chemical vapor deposition (UHVCVD). Typically, as the Ge concentration in the graded layers increases, strain fields from underlying misfit dislocations result in increased surface roughness and the formation of dislocation pileups. The generation of pileups increases the threading dislocation density in the relaxed layers. In this study the pileup formation was minimized by growing on miscut (001) substrates employing a chemical mechanical polishing (CMP) step within the epitaxial structure. Other problems such as the thermal mismatch between Si and Ge, results in unwanted residual tensile stresses and surface microcracks when the substrates are cooled from the growth temperature. Compressive strain has been incorporated into the graded layers to overcome the thermal mismatch problem, resulting in crack-free relaxed cubic Ge on Si at room temperature. The overall result of the CMP step and the growth modifications have eliminated dislocation pileups , decreased gas-phase nucleation of particles, and eliminated the increase in threading dislocation density that occurs when grading to Ge concentrations greater than 70% Ge. The threading dislocation density in the Ge layers determined through plan view transmission electron microscopy (TEM) and etch pit density (EPD) was found to be in the range of 2 x 10 6 /cm 2. Ge p-n diodes were fabricated to assess the electronic quality and prove the feasibility of high quality photodetectors on Si substrates.
2008 IEEE International Electron Devices Meeting, 2008
This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gat... more This paper describes SRAM scaling for 32nm low power bulk technology, enabled by high-K metal gate process, down to 0.149μm 2 and 0.124μm 2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, thanks to HK-MG T inv scaling. Cell read current is increased by 70% over Poly-SiON process. Ultra dense cell process window is expanded with optimized contact process. A dual-ground write assist option can additionally enable ultra dense 0.124μm 2 cell to meet low power application requirements.
2017 IEEE International Electron Devices Meeting (IEDM), 2017
We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, S... more We present a fully integrated 7nm CMOS platform featuring a 3rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um2. This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
2006 European Solid-State Device Research Conference, 2006
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size ... more This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/mum and VDD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.
MRS Proceedings, 2002
ABSTRACTIn this paper, we report the leakage current characterization of HfO2 high-k dielectric t... more ABSTRACTIn this paper, we report the leakage current characterization of HfO2 high-k dielectric thin films by using tunneling AFM, which utilizes a conducting AFM probe to detect current passing through the sample and the probe while simultaneously acquiring a topographic image. We have studied tunneling current behavior of HfO2 films by characterizing the hot spots, which are characterized by excessive local leakage current, as well as the overall current distribution. Tunneling AFM results show sensitive dependence of tunneling current with variation of film thickness. The current distribution can be described approximately by a log-normal distribution, which is consistent with the characteristics of the thickness variation. Furthermore, the film structure and thickness were also characterized with TEM and spectroscopic ellipsometry.
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2017
14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Ac... more 14nm node SRAM using FinFETs with advanced Replacement Metal Gate (RMG) module shows sensitive Access Distuib Margin (ADM) response to Local Layout Effect (LLE) as seen in planar CMOS technology using RMG [1]. Additionally, 14nm FinFET technology has more LLEs than ever due to the layout variety or tighter minimum design rule applied [2]. Fluorine with very high reaction energy diffuses from WL CONT to Pass Gate (PG) is found to lower PG Vtsat degrading ß-ratio and ADM. And, the STI stress from strap cell reduces the SRAM NFET Vtsat of the cell at the array edge degrading ADM. The natural variation of Gate-cut to PG degrades the Vth mismatch resulting in ADM degradation also. These three kinds of LLE and their impacts on ADM are discussed and analyzed in detail in this paper along with mechanisms that can cause the LLEs.
2020 IEEE International Electron Devices Meeting (IEDM), 2020
With each new node, cost and complexity of logic technology increases while being challenged to p... more With each new node, cost and complexity of logic technology increases while being challenged to provide the historical expected improvement in performance. This paper reviews the latest trends and advances in technology to enable logic scaling. Dimensional scaling, enabled by EUV lithography, will continue with advances in multi-patterning. Higher costs of EUV multi-patterning will be mitigated by high (0.55) numerical aperture (NA) EUV simplifying the patterning and potentially leading to higher yield. Logic standard cell scaling below 6-track (6T) with adequate drive current per footprint will require adoption of Gate-All-Around (GAA) device architectures, like nanosheets, along with scaling boosters like buried power rails (BPR) and semi-damascene metal integration scheme with air-gaps. Scaling below 5-track (5T) will require new compact device architectures like complementary FETs (CFETs) and alternate intra-cell interconnect layouts. Slowing SRAM scaling can also benefit from migration to BPR, forksheets and CFETs. Channels formed from 2D materials can theoretically enable gate length (Lg) and contacted poly pitch (CPP) scaling. Several new material innovations will be needed to enable 2D atomic channel transistors. Changing our view from circuits to systems, 3D integration techniques will continue to enable subsystem scaling like cache partitioning of SoCs to improve memory access. Finally, a methodology to estimate the environmental impact of technology scaling choices is proposed.
IEEE Transactions on Nuclear Science, 2017
Total ionizing dose results are provided, showing the effects of different threshold adjust impla... more Total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiationinduced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-V th transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and V th , while the low-V th transistors exhibit a larger change in offstate leakage current. The "worst-case" bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (V gs = V dd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-V th transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)
Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-8... more Extensive simulations were performed to evaluate the impact of the gate workfunction on the sub-80-nm PD and FD SOI device performance. The optimal gate workfunction for the 50 nm technology node is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS). Midgap gates are not suitable for PD SOI CMOS due to the severe short-channel
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517), 2001
MOSFETs with a zirconium dioxide (ZrO2) gate dielectric and poly-silicon gate were fabricated usi... more MOSFETs with a zirconium dioxide (ZrO2) gate dielectric and poly-silicon gate were fabricated using a low temperature CMOS process. Well-behaved transistor characteristics were obtained for devices with sizes of 14 μm×1.4 μm or smaller. Devices 14 μm×14 μm or larger were found to be nonfunctional due to the formation of Zr-silicide at the polySi-gate/Zr02 interface. In this paper, we present
2006 IEEE International Reliability Physics Symposium Proceedings, 2006
A generalized reliability model of BTI is presented where it is shown that gate stacks with simil... more A generalized reliability model of BTI is presented where it is shown that gate stacks with similar interfacial layer lie on the same NBTI vs. E-field universal curve and those with similar bulk layer lie on the same PBTI vs. E-field universal curve. From these universal curves, an optimal gate stack can be derived for which NBTI=PBTI