Steve Kang - Academia.edu (original) (raw)
Papers by Steve Kang
1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
ABSTRACT A method for parametric yield optimization which significantly reduces the simulation co... more ABSTRACT A method for parametric yield optimization which significantly reduces the simulation cost is proposed. The method assumes that the circuit performances ultimately determining yield can be approximated by computationally inexpensive functions of the inputs to the circuit simulator. These inputs are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The authors fit the approximating functions to data from a statistical experiment incurring relatively few runs of the simulator. For a given set of designable parameters, the fitted models predict the circuit performances as the uncontrollable parameters and operating conditions vary. The predictions lead to estimates of the parametric yield, which is then numerically maximized with respect to the designable parameters. The authors give a CMOS circuit example where sufficiently accurate predictions and good actual yield result from about 100 runs of the circuit simulator
Modern Physics Letters B, 2013
Boltzmann–Arrhenius–Zhurkov (BAZ) model enables one to obtain a simple, easy-to-use and physicall... more Boltzmann–Arrhenius–Zhurkov (BAZ) model enables one to obtain a simple, easy-to-use and physically meaningful formula for the evaluation of the probability of failure (PoF) of a material after the given time in operation at the given temperature and under the given stress (not necessarily mechanical). It is shown that the material degradation (aging, damage accumulation, flaw propagation, etc.) can be viewed, when BAZ model is considered, as a Markovian process, and that the BAZ model can be obtained as the steady-state solution to the Fokker–Planck equation in the theory of Markovian processes. It is shown also that the BAZ model addresses the worst and a reasonably conservative situation, when the highest PoF is expected. It is suggested therefore that the transient period preceding the condition addressed by the steady-state BAZ model need not be accounted for in engineering evaluations. However, when there is an interest in understanding the physics of the transient degradation ...
![Research paper thumbnail of Introduction to IEEE CASM Special Issue [From the Guest Editors]](https://attachments.academia-assets.com/101426136/thumbnails/1.jpg)
](IEEE Circuits and Systems Magazine, 2016
2008 Twenty-fourth Annual IEEE Semionductor Thermal Measurement and Management Symposium, 2008
The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI indu... more The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. For fast computation of surface temperature profile, Power Blurring (PB) method has been developed. This method can be applied to simulations with high spatial resolution, which have been prohibitively expensive with conventional methods. Comparative case studies with different levels of resolution illustrate that not only localized small hot spots can be overlooked but even the average chip temperature can be underestimated, and hence the necessity of thermal simulation with high spatial resolution. Using our PB method, we obtained transistor level thermal map (5×5µm 2 grid) of a 5×5mm 2 chip with a computation time of 20 seconds.
Proceedings of the 1999 international symposium on Physical design - ISPD '99, 1999
Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in hi... more Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or lass than the time of flight delay of the signal through the low resistivity interconnect. In this paper, closed form expressions for the coupling noise between adjacent interconnect are presented to estimate the coupling noise voltage on a quiet line. These expressions are based on an assumption that the interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should preferably be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.
Proceedings ED&TC European Design and Test Conference
In this paper, we present a method for nding the CMOS VLSI chip temperature p r o le and the corr... more In this paper, we present a method for nding the CMOS VLSI chip temperature p r o le and the corresponding circuit performance by using a new electrothermal simulator, ETS-A. We use a sequence o f procedures: layout extraction with x-y coordinates for individual transistors, fast timing-based p ower calculation, analytical thermal simulation using integral transform, followed by the electrothermal iterations until convergence. ETS-A takes advantage of the fast timing simulator while preserving the accuracy with use of temperature-dependent regionwise quadratic RWQ MOS transistor modeling techniques. The novel mixed 3-D & 1-D thermal simulator implemented in ETS-A e ciently takes into account the chip packaging and the thermal boundary conditions BCs, which were often ignored in typical thermal simulations. With ETS-A, on-chip temperature pro le can be c alculated and further applied to guide the temperature-driven module placement as well as chip packaging designs.
2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2020
By introducing memristors into circuit design, the limitations of traditional purely-CMOS hardwar... more By introducing memristors into circuit design, the limitations of traditional purely-CMOS hardware may be overcome. However, an extension of standard techniques for the analysis and design of conventional computing structures may be necessary to allow their applicability to the memristive counterparts. This paper adopts a generalization of the Dynamic Route Map system-theoretic concept to elucidate the mechanisms by which bio-inspired arrays of locally-coupled circuits, employing memristors with either bistable-like or analogue dynamic switching behaviours, accomplish image mem-processing tasks through the dynamical evolution of their states toward predefined equilibria.
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
ABSTRACT This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatc... more ABSTRACT This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatch on the performance degradation in high speed I/O interfaces. The impedance mismatch after ESD stressing is explained by on-chip termination resistance distortion. From the circuit-level ESD simulation and experimental results. ESD induced termination resistance degradation should be taken into consideration in the design of the high speed I/O circuits. Proposed design optimization methods of on-chip termination resistors provide sufficient safeguard against ESD damage and improve I/O signal integrity
![Research paper thumbnail of Memristors: Devices, Models, and Applications [Scanning the Issue]](https://attachments.academia-assets.com/95741200/thumbnails/1.jpg)
](Proceedings of the IEEE, 2012
CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for... more CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, ...
Signal Integrity Effects in Custom IC and ASIC Designs, 2001
Due to interactions through the common silicon substrate, the layout and placement of devices and... more Due to interactions through the common silicon substrate, the layout and placement of devices and substrate contacts can have signi cant impacts on a circuit's ESD Electrostatic Discharge and latchup behavior in CMOS technologies. Proper substrate modeling is thus required for circuit-level simulation to predict the circuit's ESD performance and latchup immunity. In this work we propose a new substrate resistance network model, and develop a novel substrate resistance extraction method that accurately calculates the distribution of injection current into the substrate during ESD or latchup events. With the proposed substrate model and resistance extraction, we can capture the three-dimensional layout parasitics in the circuit as well as the vertical substrate doping pro le, and simulate these e ects on circuit behavior at the circuit-level accurately. The usefulness of this work for layout optimization is demonstrated with an industrial circuit example.
Journal of Microelectromechanical Systems, 2004
In this paper, we present a new technique by combining the Taylor series expansion with the Arnol... more In this paper, we present a new technique by combining the Taylor series expansion with the Arnoldi method to automatically develop reduced-order models for coupled energy domain nonlinear microelectromechanical devices. An electrostatically actuated fixed-fixed beam structure with squeeze-film damping effect is examined to illustrate the model-order reduction method. Simulation results show that the reduced-order nonlinear models can accurately capture the device dynamic behavior over a much larger range of device deformation than the conventional linearized model. Compared with the fully meshed finite-difference method, the model reduction method provides accurate models using orders of magnitude less computation. The reduced MEMS device models are represented by a small number of differential and algebraic equations and thus can be conveniently inserted into a circuit simulator for fast and efficient system-level simulation.
Proceedings of the IEEE, 2006
Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (... more Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high quality, accurate thermal modeling and analysis, and thermally-oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, 2D and 3D thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. S... more Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. Sriram and SM Kang Department of Electrical and Computer Engineering Coordinated Science Laboratory and Beckman Institute University of Illinois, Urbana, IL 61801 ...
This paper looks at the current state of service protocols. With the increasing network connectiv... more This paper looks at the current state of service protocols. With the increasing network connectivity of devices, a new approach to connguring and sharing resources is needed. This paper provides an overview of the primary proposed solutions for providing these functions. After exploring the current state of network services, the relevant issues needed for the transition to this new model of computing device utilization is discussed.
Proceedings of the IEEE, 2001
Proceedings of the 11th Great Lakes Symposium on VLSI - GLSVLSI '01, 2001
Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The kee... more Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.
1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
ABSTRACT A method for parametric yield optimization which significantly reduces the simulation co... more ABSTRACT A method for parametric yield optimization which significantly reduces the simulation cost is proposed. The method assumes that the circuit performances ultimately determining yield can be approximated by computationally inexpensive functions of the inputs to the circuit simulator. These inputs are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The authors fit the approximating functions to data from a statistical experiment incurring relatively few runs of the simulator. For a given set of designable parameters, the fitted models predict the circuit performances as the uncontrollable parameters and operating conditions vary. The predictions lead to estimates of the parametric yield, which is then numerically maximized with respect to the designable parameters. The authors give a CMOS circuit example where sufficiently accurate predictions and good actual yield result from about 100 runs of the circuit simulator
Modern Physics Letters B, 2013
Boltzmann–Arrhenius–Zhurkov (BAZ) model enables one to obtain a simple, easy-to-use and physicall... more Boltzmann–Arrhenius–Zhurkov (BAZ) model enables one to obtain a simple, easy-to-use and physically meaningful formula for the evaluation of the probability of failure (PoF) of a material after the given time in operation at the given temperature and under the given stress (not necessarily mechanical). It is shown that the material degradation (aging, damage accumulation, flaw propagation, etc.) can be viewed, when BAZ model is considered, as a Markovian process, and that the BAZ model can be obtained as the steady-state solution to the Fokker–Planck equation in the theory of Markovian processes. It is shown also that the BAZ model addresses the worst and a reasonably conservative situation, when the highest PoF is expected. It is suggested therefore that the transient period preceding the condition addressed by the steady-state BAZ model need not be accounted for in engineering evaluations. However, when there is an interest in understanding the physics of the transient degradation ...
IEEE Circuits and Systems Magazine, 2016
2008 Twenty-fourth Annual IEEE Semionductor Thermal Measurement and Management Symposium, 2008
The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI indu... more The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. For fast computation of surface temperature profile, Power Blurring (PB) method has been developed. This method can be applied to simulations with high spatial resolution, which have been prohibitively expensive with conventional methods. Comparative case studies with different levels of resolution illustrate that not only localized small hot spots can be overlooked but even the average chip temperature can be underestimated, and hence the necessity of thermal simulation with high spatial resolution. Using our PB method, we obtained transistor level thermal map (5×5µm 2 grid) of a 5×5mm 2 chip with a computation time of 20 seconds.
Proceedings of the 1999 international symposium on Physical design - ISPD '99, 1999
Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in hi... more Interconnect between a CMOS driver and receiver can be modeled as a lossy transmission line in high speed CMOS VLSI circuits as transition times become comparable to or lass than the time of flight delay of the signal through the low resistivity interconnect. In this paper, closed form expressions for the coupling noise between adjacent interconnect are presented to estimate the coupling noise voltage on a quiet line. These expressions are based on an assumption that the interconnections are loosely coupled, where the effect of the coupling noise on the waveform of the active line is small and can be neglected. It is demonstrated that the output impedance of the CMOS driver should preferably be comparable to the interconnect impedance in order to reduce the propagation delay of the CMOS driver stage.
Proceedings ED&TC European Design and Test Conference
In this paper, we present a method for nding the CMOS VLSI chip temperature p r o le and the corr... more In this paper, we present a method for nding the CMOS VLSI chip temperature p r o le and the corresponding circuit performance by using a new electrothermal simulator, ETS-A. We use a sequence o f procedures: layout extraction with x-y coordinates for individual transistors, fast timing-based p ower calculation, analytical thermal simulation using integral transform, followed by the electrothermal iterations until convergence. ETS-A takes advantage of the fast timing simulator while preserving the accuracy with use of temperature-dependent regionwise quadratic RWQ MOS transistor modeling techniques. The novel mixed 3-D & 1-D thermal simulator implemented in ETS-A e ciently takes into account the chip packaging and the thermal boundary conditions BCs, which were often ignored in typical thermal simulations. With ETS-A, on-chip temperature pro le can be c alculated and further applied to guide the temperature-driven module placement as well as chip packaging designs.
2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2020
By introducing memristors into circuit design, the limitations of traditional purely-CMOS hardwar... more By introducing memristors into circuit design, the limitations of traditional purely-CMOS hardware may be overcome. However, an extension of standard techniques for the analysis and design of conventional computing structures may be necessary to allow their applicability to the memristive counterparts. This paper adopts a generalization of the Dynamic Route Map system-theoretic concept to elucidate the mechanisms by which bio-inspired arrays of locally-coupled circuits, employing memristors with either bistable-like or analogue dynamic switching behaviours, accomplish image mem-processing tasks through the dynamical evolution of their states toward predefined equilibria.
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
ABSTRACT This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatc... more ABSTRACT This paper reports the effect of electrostatic discharge (ESD) induced impedance mismatch on the performance degradation in high speed I/O interfaces. The impedance mismatch after ESD stressing is explained by on-chip termination resistance distortion. From the circuit-level ESD simulation and experimental results. ESD induced termination resistance degradation should be taken into consideration in the design of the high speed I/O circuits. Proposed design optimization methods of on-chip termination resistors provide sufficient safeguard against ESD damage and improve I/O signal integrity
Proceedings of the IEEE, 2012
CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for... more CMOS Digital Integrated Circuits: Analysis and Design is the most complete book on the market for CMOS circuits. Appropriate for electrical engineering and computer science, this book starts with CMOS processing, and then covers MOS transistor models, basic CMOS gates, ...
Signal Integrity Effects in Custom IC and ASIC Designs, 2001
Due to interactions through the common silicon substrate, the layout and placement of devices and... more Due to interactions through the common silicon substrate, the layout and placement of devices and substrate contacts can have signi cant impacts on a circuit's ESD Electrostatic Discharge and latchup behavior in CMOS technologies. Proper substrate modeling is thus required for circuit-level simulation to predict the circuit's ESD performance and latchup immunity. In this work we propose a new substrate resistance network model, and develop a novel substrate resistance extraction method that accurately calculates the distribution of injection current into the substrate during ESD or latchup events. With the proposed substrate model and resistance extraction, we can capture the three-dimensional layout parasitics in the circuit as well as the vertical substrate doping pro le, and simulate these e ects on circuit behavior at the circuit-level accurately. The usefulness of this work for layout optimization is demonstrated with an industrial circuit example.
Journal of Microelectromechanical Systems, 2004
In this paper, we present a new technique by combining the Taylor series expansion with the Arnol... more In this paper, we present a new technique by combining the Taylor series expansion with the Arnoldi method to automatically develop reduced-order models for coupled energy domain nonlinear microelectromechanical devices. An electrostatically actuated fixed-fixed beam structure with squeeze-film damping effect is examined to illustrate the model-order reduction method. Simulation results show that the reduced-order nonlinear models can accurately capture the device dynamic behavior over a much larger range of device deformation than the conventional linearized model. Compared with the fully meshed finite-difference method, the model reduction method provides accurate models using orders of magnitude less computation. The reduced MEMS device models are represented by a small number of differential and algebraic equations and thus can be conveniently inserted into a circuit simulator for fast and efficient system-level simulation.
Proceedings of the IEEE, 2006
Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (... more Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high quality, accurate thermal modeling and analysis, and thermally-oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, 2D and 3D thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described.
Proceedings of the 30th international on Design automation conference - DAC '93, 1993
Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. S... more Page 1. Fast Approximation of the Transient Response of Lossy Transmission Line 'Ikees* M. Sriram and SM Kang Department of Electrical and Computer Engineering Coordinated Science Laboratory and Beckman Institute University of Illinois, Urbana, IL 61801 ...
This paper looks at the current state of service protocols. With the increasing network connectiv... more This paper looks at the current state of service protocols. With the increasing network connectivity of devices, a new approach to connguring and sharing resources is needed. This paper provides an overview of the primary proposed solutions for providing these functions. After exploring the current state of network services, the relevant issues needed for the transition to this new model of computing device utilization is discussed.
Proceedings of the IEEE, 2001
Proceedings of the 11th Great Lakes Symposium on VLSI - GLSVLSI '01, 2001
Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The kee... more Dynamic logic is much susceptible to noise, specially in ultra deep submicron technology. The keeper transistor has to be carefully sized to maintain noise margin without much speed penalty. In this paper, we analyze the keeper transistor sizing with respect to the size of NMOS transistors in the evaluation tree. Based on the analytical results, we propose a keeper transistor sizing method. HSPICE simulation results show that the proposed keeper transistor sizing method can be broadly applied to all domino logic gates.