T.C Thanuja - Academia.edu (original) (raw)

Papers by T.C Thanuja

International Journal of Innovative Technology and Exploring Engineering, 2019

The spectrum scarcity problem is addressed by number solutions by various researchers in cognitiv... more The spectrum scarcity problem is addressed by number solutions by various researchers in cognitive network field. The dynamic spectrum allocation using cooperative spectrum sensing is required to analyze with respect to errors present in detection due to fixed threshold. The spectrum allocation on the basis of demand may involve the priority based requests for spectrum allocation. The contribution of this paper is for evaluating the performance of dynamic threshold energy detection schemes which are error dependent and hence minimization of errors. The performance evaluation of two methods with error minimization strategy are evaluated and results are compared to know the performance oriented dependency parameters in dynamic threshold methods and to provide the platform strategy for energy optimization in cooperative sensing.

2020 International Conference on Emerging Smart Computing and Informatics (ESCI), 2020

The wireless communication is a backbone for a development of a nation. But spectrum is finite re... more The wireless communication is a backbone for a development of a nation. But spectrum is finite resource and issues like spectrum scarcity, loss of signal quality, transmission delay, raised in wireless communication system due to growth of wireless applications and exponentially increased number of users. Secondary use of a spectrum using Software Defined Radio (SDR) is one of the solutions which is also supported by TRAI. The spectrum sensing is key process in communication based on secondary use of spectrum. But energy consumption, added delay, primary users security are some threats in this system. Here in this paper we mainly focused on throughput optimization in secondary use of spectrum based on optimal sensing time and number of Secondary users during cooperative spectrum sensing in Cognitive radio networks.

2021 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON)

Watermarking audio files has recently become the focus of much attention. This is primarily due t... more Watermarking audio files has recently become the focus of much attention. This is primarily due to faster data transmission rates on the Internet, which has allowed illegal usage of digital audio files. Watermarking may give recording companies the ability to enforce copyright protection of their products. The requirements of watermarking audio lie in preserving the file quality (imperceptibility) and remain intact after a number of file damaging operations (robustness). The main challenge in digital audio watermarking is to achieve the right tradeoff between the mutually exclusive goals of robustness and high watermark data rate. This paper gives a performance evaluation of popular audio watermarking schemes in prevalence today. A system simulation of selected schemes has been performed in MAT LAB. Key words: Intellectual property, audio watermarking, digital rights management.

2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI), 2017

Today growth of wireless applications and number of users is exponential and with fact of finite ... more Today growth of wireless applications and number of users is exponential and with fact of finite availability of spectrum; spectrum scarcity, congestion, loss of signal quality are important issues in wireless communication. Spectrum Sensing and secondary use of spectrum is a upcoming solution for spectrum scarcity, but Spectrum Sensing creates burden on energy consumption as well as time limits of wireless nodes. This paper addresses about factors affecting on Cooperative Spectrum Sensing and review of techniques used to optimize delay and energy consumption.

This paper proposes a novel scheme of presenting high dynamic range images on low dynamic range d... more This paper proposes a novel scheme of presenting high dynamic range images on low dynamic range displays using gamma correction based tone mapping and guided image filtering. The typical high dynamic range image is split into base layer and detail layer using guided image filter. Dynamic range of the base layer is compressed or expanded using gamma correction method. The gamma correction with different gamma coefficients are applied to the image to generate gamma compressed and gamma expanded images. Then both the images are combined according to the weight functions based on local variances. The local variances are used as local weights to bring out the detail information. Guided image filter computes the filtering output by considering the content of the guidance image, which can be input image itself or any other image. The guided filter is used as edge preserving smoothing operator. Finally detail layer of the guided image filter is added to the output image obtained from gamma ...

Imperial journal of interdisciplinary research, 2016

The Phase lock loop (PLL) is mainly used for generating on chip clock pulses in digital circuits.... more The Phase lock loop (PLL) is mainly used for generating on chip clock pulses in digital circuits. The most important application of PLL is clock generation & recovery in microprocessor, frequency synthesizer. In this paper the PLL is designed as a frequency synthesizer for producing high frequency range and it is designed for ZigBee application with its center frequency of 2.41GHz.The PLL system designed using 45nm coms technology in CADENCE Virtuoso IC 6.1.6. The voltage controlled oscillator (VCO) is heart of the PLL, in this, have used five stage current starved VCO (CSVCO) to achieve lower chip area, less power consumption and to get the tuning rage of CSVCO in 0.099-5.578 GHz. Found wide lock in range is 850 GHz and the PLL has a faster lock in time of 60.23 ns. The layout of the PLL is drawn in CADENCE Virtuoso Layout Editor. The power consumption of PLL system is 99.20 µW.

Summary Watermarking audio files has recently become the focus of much attention. This is primari... more Summary Watermarking audio files has recently become the focus of much attention. This is primarily due to faster data transmission rates on the Internet, which has allowed illegal usage of digital audio files. Watermarking may give recording companies the ability to enforce copyright protection of their products. The requirements of watermarking audio lie in preserving the file quality (imperceptibility) and remain intact after a number of file damaging operations (robustness). The main challenge in digital audio watermarking is to achieve the right tradeoff between the mutually exclusive goals of robustness and high watermark data rate. This paper gives a performance evaluation of popular audio watermarking schemes in prevalence today. A system simulation of selected schemes has been performed in MAT LAB.

Packet classification is the critical task in networking and it is used by network processor pres... more Packet classification is the critical task in networking and it is used by network processor present in router to classify the packets according to the header field values. Packet classification is the process of matching packet header values to the rule header values. The packet is processed according to the matched rule. The contribution of this paper is “ Pipelined packet classification” architecture using hyper cut algorithm. This architecture is based on building the decision tree. The pipelined architecture for packet classification reduces the critical delay and gives high throughput of 3.98 Gbps.

Low power design has become the major challenge of present chip designs as leakage power has been... more Low power design has become the major challenge of present chip designs as leakage power has been rising with scaling of technologies. As the demand for low power and low cost increases, it is very important to design low power, high performance, and fast responding SRAM (Static Random Access Memory) since they are critical component in high performance processors. The Conventional 6T SRAM cell is very much prone to noise during read operation[2]. To overcome the problems in 6T SRAM cell, researchers have proposed different SRAM topologies such as 8T, 9T, 10T etc. bit cell design. These designs can improve the cell stability but suffer from bit line leakage noise. Dynamic power was previously the single largest concern for low-power chip designers, but as the feature size shrinks, the leakage power reduction has become the great challenge for current and future technologies. In this paper, different SRAM cells are used for the power analysis and also single ended 6T SRAM is introduc...

All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and c... more All Digital Phase Lock Loop (ADPLL) is contributing in advancement in digital communication and control system since 1980. In this paper “High speed ADPLL for FM application” is proposed. The ADPLL is designed using phase detector, digital loop filter and increment-decrement counter. Here the speed of ADPLL is increased by using novel multiplexer based increment– decrement counter. The ADPLL using these blocks are simulated by using Xilinx 14.5. It is observed that the delay of proposed ADPLL is less compare to existing ADPLL [1]. Further, the proposed ADPLL is used to generate FM modulation by using interpolator method.

Rapid industrialization and urbanization cause the continuous decline in the environmental qualit... more Rapid industrialization and urbanization cause the continuous decline in the environmental quality parameters. Today, the world is facing a challenge like global warming which occurs when carbon dioxide (CO2) and other greenhouse gases accumulate in the atmosphere and absorb sunlight and solar emission that have bounced off the earth’s surface. Its impacts are sea level rise, changes in the seasonal patterns, rising temperature, more frequent droughts, and extreme rainfalls. Air pollutions’ serious impact on human health and environment requires worldwide awareness and understanding. Existing systems gives real-time air pollution data to pollution monitoring authorities and, these systems are having fixed infrastructure with maintenance, reconfiguration, and reduced sensing issues. Conventional measurements are costly methods and spatially restricted. Therefore, air pollution monitoring becomes a challenging task. Here, we propose Wireless Sensor Network (WSN) based system with low-...

The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provid... more The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multi-media processing. As the multimedia applications are growing rapidly past a decade. The applications of multi-media for processing high resolution video, data and audio sequences are known to require a high speed and high-density memory port. The memory is required for data storage in real time applications, the memory controllers support DDR3/DDR2/DDR/SDRAM memories and it can be configured according to their requirements. In spite much research on performance improvement, the external memory performance is lagging. Hence the memory controller is essential. The proposed architecture of multiport memory controller is designed for flexible communication between the master and the slave ports and also the communication speed is increased as the design contains a number of buffers for, and also embedded memory for configura...

This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 1... more This paper signifies the transient analysis of the PLL and is implemented in cadence tool using 180nm technology node. Frequency is expected to be in GHz range for present communication systems to increase the speed and therefore PLL is designed to produce the frequency in GHz range. The designed PLL consists of Phase frequency detector/Charge pump (PFD/CP), second order Low pass filter (LPF) and Schmitt trigger based current starved voltage controlled oscillator (CSVCO). PLL is designed to achieve a stable frequency output. The designed PLL produces 1.084 GHz with 2.382mW of average power consumption.

This paper focuses on monitoring the amount of usage of water in the milk processing unit and gen... more This paper focuses on monitoring the amount of usage of water in the milk processing unit and generates report of the daily water usage in each processing section. The system keeps track of the purchased water, water in reservoir and overall usage of water in the milk industry. The flow sensors will sense the flow of water in each pipe which ultimately tells the usage of water at one block ideally. The level sensor senses the level of water into the reservoir and tells the availability of water into the reservoir. This water usage data would be sent to the cloud using the Internet of Things (IoT) space. The cloud data is computed and generates pattern of the data input and provides a detailed water consumption chart on the desktop as well as smart phones.

International Journal of Engineering & Technology

Perceptibility and robustness are two incongruous requirements demanded by digital image watermar... more Perceptibility and robustness are two incongruous requirements demanded by digital image watermarking for digital right management and other applications. A realistic way to concurrently satisfy the two contradictory requirements is to use robust watermark algorithm. The developed algorithm uses DTCWT and PCA techniques to embed watermark signal in host signal. To prove the algorithm robustness without much affecting perceptibility several attacks like noises, cropping, blurring, rotation are applied and tested by varying attack parameters. Parameters like Peak signal noise ratio and Correlation Coefficient are calculated for each attack. Attack percentage is varied and performance parameters are calculated to prove the robustness of the developed algorithm.

2016 International Conference on Computation System and Information Technology for Sustainable Solutions (CSITSS), 2016

Multi Mobile agents concept is the key technology used to optimize energy consumption in wireless... more Multi Mobile agents concept is the key technology used to optimize energy consumption in wireless sensor networks. Two kinds of mobile agents are used here link agent and data agent. First one takes care of the new addition of sensor nodes, disconnections in network and the other connectivity issues and the latter takes part in actual data transfer between sensor nodes and Sink node. Implementation is done by clustering the network and then ensuring the network connectivity using link agent. Further cluster heads will determine the assignment of sensor nodes to each mobile agent considering its data amount and absolute distance from cluster head. To achieve the above, Farthest Node First Nearest Node Next algorithm is presented and its efficiency is discussed. As the presented algorithm takes care of distance, itinerary can be planned in the same order as the assignment to each mobile agent. This approach has a greater impact in terms of task duration and itinerary planning.

International Journal of Science and Research (IJSR), 2016

Digital multipliers are the most critical part of the digital systems. The overall performance of... more Digital multipliers are the most critical part of the digital systems. The overall performance of the Digital system depends on the speed of the multipliers. Due to Aging effects like negative bias temperature instability in pMOS transistor when it is under negative bias, increases the threshold voltage of the transistor hence the speed of the multiplier reduces, a similar positive bias temperature instability effect occurs in nMOS transistor, when it is under positive bias. Hence it is required to design a reliable low power high performance multiplier. In this paper we propose a Razor based low power multiplier with variable latency design. In this multiplier the performance degradation due to the aging effect can be minimized using Adaptive Hold Logic. This logic is applied to column and row bypassing multipliers.