Thomas Toifl - Academia.edu (original) (raw)

Papers by Thomas Toifl

IEEE Journal of Solid-State Circuits, 2000

ABSTRACT This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip ... more ABSTRACT This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28 Gb/s is 693 mW/lane.

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015

Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 2015

The 16th Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2003. LEOS 2003., 2003

We identify applications for optics-enabled printed circuit boards, together with a list of requi... more We identify applications for optics-enabled printed circuit boards, together with a list of requirements that have to be met for real-world products. We draw conclusions for the technology choices, and present our approaches and experiments.

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is present... more A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is presented. Capacitive bandwidth and group-delay enhancements are combined with series peaking in a shunt-peaking amplifier. The circuit occupies 0.02mm2 and dissipates 57mW at 1V

2012 Symposium on VLSI Circuits (VLSIC), 2012

This paper describes a low-power implementation of a receiver data path, consisting of the RX ter... more This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <10 -12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS ... more A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Source-series-terminated (SST) drivers offer the advantage of providing a large range of terminat... more Source-series-terminated (SST) drivers offer the advantage of providing a large range of termination voltages, making them particularly suitable for multi-standard I/Os [1, 2]. Many standards (e.g. [3]) however, call for larger vertical eye openings that require raising the dc supply voltage from the 1.0V limit for thinoxide devices in 65nm technology to 1.2 or 1.5V. These requirements are addressed in the proposed SST transmitter design by combining a thin-oxide pre-driver stage running at 1.0V followed by thick-oxide output stages operated at 1.5V. Key features of this design include the implementation of tri-statable output slices consisting of programmable binary-weighted pre-distortion slices to achieve a mutually independent adjustment of the impedance tuning and FIR-based transmitter equalization, the level shifter design and the application of T-coils [4] that enable a broad-band impedance matching with a return loss of -16dB over 10GHz bandwidth. Moreover, the transmitter is capable to suppress the clock duty-cycle distortion by a factor of 5×.

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015

IEEE Journal of Solid-State Circuits, 2000

ABSTRACT This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip ... more ABSTRACT This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28 Gb/s is 693 mW/lane.

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015

Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 2015

The 16th Annual Meeting of the IEEE Lasers and Electro-Optics Society, 2003. LEOS 2003., 2003

We identify applications for optics-enabled printed circuit boards, together with a list of requi... more We identify applications for optics-enabled printed circuit boards, together with a list of requirements that have to be met for real-world products. We draw conclusions for the technology choices, and present our approaches and experiments.

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006

A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is present... more A DC-to-44GHz amplifier with 19dB differential gain in a standard 90nm CMOS technology is presented. Capacitive bandwidth and group-delay enhancements are combined with series peaking in a shunt-peaking amplifier. The circuit occupies 0.02mm2 and dissipates 57mW at 1V

2012 Symposium on VLSI Circuits (VLSIC), 2012

This paper describes a low-power implementation of a receiver data path, consisting of the RX ter... more This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <10 -12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.

2010 IEEE International Solid-State Circuits Conference - (ISSCC), 2010

A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS ... more A 23 (22 data+1 clk) lane source-synchronous RX PHY for server systems is realized in 65 nm CMOS supporting FB-DIMM 2 and QP11.0 multiple link protocols at 4.8-6.4 Gb/s. To minimize jitter, either a poly-phase filter or clean-up PLL can be selected for l/Q clock generation. Power consumption of 4.5 mW/Gb/s is achieved in the product-level design by a pulsed

2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2008

Source-series-terminated (SST) drivers offer the advantage of providing a large range of terminat... more Source-series-terminated (SST) drivers offer the advantage of providing a large range of termination voltages, making them particularly suitable for multi-standard I/Os [1, 2]. Many standards (e.g. [3]) however, call for larger vertical eye openings that require raising the dc supply voltage from the 1.0V limit for thinoxide devices in 65nm technology to 1.2 or 1.5V. These requirements are addressed in the proposed SST transmitter design by combining a thin-oxide pre-driver stage running at 1.0V followed by thick-oxide output stages operated at 1.5V. Key features of this design include the implementation of tri-statable output slices consisting of programmable binary-weighted pre-distortion slices to achieve a mutually independent adjustment of the impedance tuning and FIR-based transmitter equalization, the level shifter design and the application of T-coils [4] that enable a broad-band impedance matching with a return loss of -16dB over 10GHz bandwidth. Moreover, the transmitter is capable to suppress the clock duty-cycle distortion by a factor of 5×.

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015