A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS (original) (raw)
Related papers
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER 10 12 was significantly increased with the use of DFE for short-to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.
IEEE Journal of Solid-State Circuits, 2011
A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s. Index Terms-Adaptive floating-tap decision feedback equalizer, baseline wander correction, multi-media transceiver, PLL with wide frequency tuning range, source-series terminated driver.
IEEE Journal of Solid-State Circuits, 2000
A 14.025 Gb/s multi-media transceiver employs on-die Rx AC coupling with baseline wander correction and equalizes up to 26 dB insertion loss at 14.025 Gb/s with a linear equalizer, 10-tap DFE, and 4-tap Tx FIR filter in SST driver. The proposed techniques enable direct feedback for 1st-tap ISI cancellation, and positions of four DFE taps to be adapted over the range of 7 to 38 UI. The prototype is realized in 40 nm CMOS, consumes 410 mW at worst case, and has passed 16GFC compliance tests at 14.025 Gb/s. Index Terms-Adaptive floating-tap decision feedback equalizer, baseline wander correction, multi-media transceiver, PLL with wide frequency tuning range, source-series terminated driver.
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2013
A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is halfrate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER < 10 ) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.
IEICE Electronics Express
This paper describes quad-rate 1-FIR 2-IIR decision feedback equalizer (DFE) with summer reduction technique for high-speed serial communication in a 65 nm CMOS technology. The proposed DFE halves the number of summers by using resettable slicer and summer with multiplexer. Therefore, the proposed DFE reduces power consumption significantly because summer dissipates a lot of power. The DFE that is verified by pre-layout simulations achieved 0.69 unit-interval (UI) eye-opening. The proposed DFE that is designed with a 65-nm technology operates at 28 Gb/s and occupies 0.023 mm 2. Finally, the power efficiency of the proposed DFE is 0.88-pJ/bit.
A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS
2012
To overcome the limited bandwidth of chip-to-chip and backplane communication channels at multi-Gb/s data-rates, high-speed I/O transceivers employ a combination of DFE in the RX and FFE in the TX, since these equalizers complement each other to provide an effective equalization solution. Using RX-side FFE instead of TX-side FFE can bring important advantages to the transceiver: it obviates any back-channel for coefficient adaptation and improves RX interoperability with different TXs. RX-FFE is also preferable to simple peaking amplifiers, since it enables greater flexibility in setting the pre-cursor and post-cursor coefficients. However, traditional RX-FFEs with analog delay lines are not area efficient and do not support a wide range of data-rates. This paper describes design techniques that enable the realization of a RX with 4-tap FFE and 5-tap DFE, having area and power efficiency comparable to DFE-only RXs.
A 40-Gb/s serial link transceiver in 28-nm CMOS technology
2014 Symposium on VLSI Circuits Digest of Technical Papers, 2014
A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit equalization consists of a 2-tap feed-forward equalizer (FFE) while receive equalization includes a 2-tap FFE using a transversal filter, a 3-stage continuous-time linear equalizer with active feedback, and discrete-time equalizers consisting of a 17-tap decision feedback equalizer (DFE) and a 3-tap sampled FFE. The receiver uses quarter-rate double integrate-and-hold sampling. The clock and data recovery (CDR) unit uses a split-path CDR/DFE design which facilitates wider bandwidth and lower jitter simultaneously. A phase detection scheme that filters out edges affected by residual inter-symbol interference allows recovering a low-jitter clock from a partially-equalized eye. A fractional-N PLL is implemented for frequency offset tracking. Combining these techniques, the digital CDR recovers a stable 10 GHz clock from an eye containing 0.8 UI p-p input jitter and achieves 1-10 MHz of tracking bandwidth. The transceiver achieves horizontal and vertical eye openings of 0.27 UI and 120 mV, respectively, at BER = 10-9. The quad SerDes is realized in 28 nm CMOS technology. Amortizing common blocks, it occupies 0.81 mm per lane and achieves 23.2 mW/Gb/s power efficiency at 40 Gb/s. Index Terms-Active feedback continuous-time linear equalizer, chip-to-chip communications, current-integrating DFE summer, decision feedback equalizer (DFE), distributed ESD protection structure, high-speed serial link (SerDes), receive-side feed-forward equalizer (RX-FFE), split-path clock and data recovery (split-path CDR), transversal filter, wireline transceiver.
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology
IEEE Journal of Solid-State Circuits, 2000
This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200 mVppd, one transmitter/receiver pair and one PLL consume 300 mW.
A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE
IEEE Journal of Solid-State Circuits, 2014
A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a precursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15-22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.