Sukeshni Tirkey - Academia.edu (original) (raw)

Papers by Sukeshni Tirkey

A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-p... more A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-power digital circuitry has been proposed in this study. This study examines the effects of several dielectric insulators used as gate materials, silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), and zirconium dioxide (ZrO2). The device's performance parameters are enhanced by utilizing different dielectrics in MOSFETs as a gate dielectric since the leakage current is significantly decreased. Following the validation of simulation findings using MOSFET reference data, the structure is evaluated by 15nm and 20nm node technology. In particular 15 nm scale, MOSFET exhibits reduced IOFF, higher ION/IOFF ratio, enhanced Drain Induced Barrier Lowering (DIBL), and Sub-threshold Slope (SS). For proposed MOSFETs, the simulated values of ION, IOFF, ION/IOFF, SS, DIBL, TGF, output conductance (gd), intrinsic gain (Av), and early voltage (VEA) shows improvements which are h...

2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), 2017

Ambipolar conduction is a subject of grave concern for the steep subthreshold slope tunnel field-... more Ambipolar conduction is a subject of grave concern for the steep subthreshold slope tunnel field-effect transistor (TFET) to use it in CMOS circuits. For this, we present a graded channel TFET (GD TFET) to suppress the ambipolar nature of device for wide span of gate to source voltage. Regarding this, half of the channel portion adjacent to source is considered lightly doped whereas, remaining half of the channel portion near to drain is considered heavily doped which modulates the energy bands at the drain channel interface. This leads to disturbance in the abruptness of bands at drain/channel junction resulting into poor band to band tunneling generation rate, hence reduced ambipolar nature of the device is obtained. The device behaviour is compared with the conventional TFET and optimization of heavily doped channel section length is also presented.

2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), 2017

In this paper, investigation for different configurations of N-type Hetero Junction Double Gate T... more In this paper, investigation for different configurations of N-type Hetero Junction Double Gate Tunnel Field-Effect Transistor (HJ-TFET) with Dual metal gate work function and hetero gate dielectric material along with gate underlap is performed to achieve improvements in DC and analog/RF performances. In this regard, the creation of hetero-junction using band gap engineering maintains the lower energy band and higher energy band at source/channel and drain/channel interface respectively to provide high ON current and low ambipolar behavior. A high-density layer of N+ type concentration is added at source/channel junction to obtain abruptness at the same. Further, application of work function engineering on the gate electrode over the channel specified as Tunnel gate (M1) towards the source region and Auxiliary gate (M2) towards the drain region facilitates to achieve higher ON-state current at the cost of poor analog/RF responses. In this concern, hetero gate dielectric and gate under-lap concepts are implied to reduce parasitic capacitances which enhance RF performance of the device. Furthermore, optimization of work function for tunnel gate and the auxiliary gate has been performed to assess the optimum values of work function.

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017

This manuscript presents a detailed study of Hetero Junction Dual Gate Tunnel Field Effect Transi... more This manuscript presents a detailed study of Hetero Junction Dual Gate Tunnel Field Effect Transistor (HJDG-TFET) for improving the drain current and degrading the ambipolar behavior. The proposed device employs heteromaterial for device analysis. Drain current of the device increases because of narrowing of tunneling barrier width at the sourcechannel junction with the application of low band gap material at the source/channel junction. Hence, the proposed device shows superior performance over conventional DG-TFET in terms of sub threshold slope, drain current, resistant to parasitic capacitance and high frequency parameters. Further, the optimization of channel length and drain voltage is also performed to ensure the reliability of the device. Hence, the overall performance of the HJ-DG-TFET is examined for better efficiency of the device.

IEEE Sensors Journal, 2020

The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-... more The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-2 in terms of spike, envelope and DNA proteins of the virus. The models used in a simulation and the transfer characteristic of the proposed sensor both are first calibrated with the fabricated FET sensor. Than the modification of low workfunction Hf Gate2 (dual metal control gate) has been proposed in the manuscript. The extended Hf Gate2 provides more space for immobilization of the virus proteins and utilize the advantages of charge plasma formation and electrical doping. In the manuscript, sensitivity of the proposed sensor has been investigated by DC and RF parameters in terms of virus proteins and their charge densities. In addition, a comparative analysis of the proposed sensor with and without Hf Gate2 has been examined in terms of DC/RF parameters that reveal a significance of the proposed modification. Moreover, the Impact of replacement of SiO2 insulating layer by HfO2 has also been studied over the sensing ability of sensor in the context of DC/RF components.

Applied Physics A, 2019

In this research, to achieve steep subthreshold slope, high I on ∕I off ratio and low ambipolarit... more In this research, to achieve steep subthreshold slope, high I on ∕I off ratio and low ambipolarity in TFETs, we have proposed a device which consists of metal strips near drain-channel and source-channel interfaces. The proposed device is named as dual metal-strip charge plasma-based junction-less tunnel FET (DMS-CP-JL-TFET), which will improve the device performance in terms of DC and analog/RF figure of merits (FOMs). The introduction of a metal strip near the drain-channel interface which produces a wider energy gap reduces ambipolarity, while the metal strip near the source-channel interface delivers abruptness at the junction, leading to a better subthreshold slope and higher I on ∕I off ratio. Also, positive trap charge (PTC) is taken in the simulations, because the proposed devices have shown great improvement in the presence of PTC, which has also been discussed in this work. In supporting our work, we have added the optimization part for metal strips (M1 and M2) in terms of work functions, lengths to achieve better electrical characteristics.

IEEE Transactions on Electron Devices, 2018

A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP T... more A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p + substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n + drain and intrinsic channel regions. This creates abruptness and reduces the barrier at the source/channel interface of CP TFET, which improves the dc characteristics of the device. Furthermore, the drain electrode is separated into two sections and applied with dual work function, which reduces the ambipolar behavior, parasitic capacitance, and enhances radio frequency parameters. The crux of the script is to advance the performance of the device while maintaining the classical CMOS fabrication flow with its inherent advantages by using p + substrate initially. To analyze the performance, a comparison between conventional CP TFET and dual drain electrode CP TFET (proposed) is shown at the simulation level. Optimization of length and workfunction of the section of drain electrode adjacent to the channel is demonstrated to assess the desired ON-current and ambipolarity of the device. Furthermore, the device performance is examined with the application of multigate work function and heterogate dielectric engineering to achieve more improvements in device performance.

Micro & Nano Letters, 2018

In this work, the authors have focused on increasing the current driving capability, speed of ope... more In this work, the authors have focused on increasing the current driving capability, speed of operation, suppression of parasitic capacitance and ambipolarity of the charge plasma tunnel field effect transistor (CPTFET). Gate dielectric and hetero-material engineering are employed in the CPTFET to obtain better drain current. Introduction of high-k dielectric increases the injection of charge carriers in the intrinsic body while a low-energy bandgap III-V material reduces the tunnelling width leading to the increased rate of band-to-band tunnelling of electrons and thus, enhancing the ON-state current of the device. Hence, the proposed device shows superior performance when operated in regime of DC and high frequency. For reducing the ambipolar conduction in the device, a widely used concept of underlapping of gate electrode is employed which reduces the leakage current in the device. Further, to determine the reliability of the device at high frequency, an analysis of linearity parameters is carried out. The proposed device is highly reliable to function at high-frequency regime. Therefore, the overall introduction of gate dielectric engineering, hetero-material engineering and underlapping of gate electrode improves the performance and characteristics of CPTFET.

Microelectronic Engineering, 2018

Applied Physics A, 2018

Ambipolarity in tunnel field-effect transistor (TFET) is a subject of grave concern in the curren... more Ambipolarity in tunnel field-effect transistor (TFET) is a subject of grave concern in the current scenario of the semiconductor industry as this property of device limits its usability in CMOS circuit applications. In this concern, this paper presents a new approach to suppress the ambipolar behavior of dopingless TFET (DL TFET) by controlling the lateral band-to-band tunneling at the drain/channel interface. To execute this, a metal strip is embedded inside the oxide region between gate and drain terminals to modulate the energy bands for preventing the tunneling of charge carriers. The energy bands are widened at the drain-channel junction using this technique and correspondingly ambipolarity is reduced by a factor of 10 11. The variation in the energy bands is examined under different negative gate bias for the proposed device and conventional device which has shown that the energy barrier for the proposed device remains wider for different voltages under the influence of metal embedded. Alignment of the metal strip is varied to obtain the desired performance of the device. In this regard, optimization of work function and length of metal strip along with its position is demonstrated considering its impact on the ambipolar current and ON-state current, which gave 4.0 eV work function and 20 nm as the optimized work function and length of the metal strip, respectively.

Superlattices and Microstructures, 2017

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET... more Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance, Superlattices and Microstructures (2017),

IEEE Transactions on Electron Devices, 2017

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for ach... more Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current (I on) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving I on , point subthreshold swing and threshold voltage (V th). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

Journal of Computational Electronics, 2017

This paper presents a comparative analysis of the combined effects of gate underlapping and dual ... more This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of SiO 2 as the gate dielectric. Therefore, a het-B Dharmendra Singh Yadav

Superlattices and Microstructures, 2017

Investigation of gate material engineering in junctionless TFET to overcome the trade-off between... more Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics, Superlattices and Microstructures (2017),

Journal of Computational Electronics, 2017

Achieving steeper subthreshold slope and high ON–OFF current ratio ($$I_{\mathrm{ON}}/I_{\mathrm{... more Achieving steeper subthreshold slope and high ON–OFF current ratio ($$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF) is essential for use of semiconductor devices in switching applications. It is well known that tunnel field-effect transistors face serious issues related to low ON-state current and poor radio frequency (RF) response. We report herein a unique method for realizing a sharp tunneling junction in a charge plasma-based junctionless tunnel field-effect transistor by embedding a metal strip in the oxide region near to the source–channel connection. This modulates the carrier concentration profile at the source–channel interface, making it abrupt. This steeper source–channel tunneling junction results in a reduced tunneling barrier and increased flow of charge carriers at the junction. Furthermore, electron transfer along the channel is accounted for using postprocessing based on the drift–diffusion equations as well as the band-to-band tunneling current. This phenomenon contributes to the improved direct-current (DC) characteristics of the device. Selection of a metal with an appropriate work function for the strip can improve the subthreshold swing and threshold voltage ($$V_{\mathrm{th}}$$Vth) of the device. The increased charge carrier tunneling rate at the junction also results in a huge improvement in RF parameters of the device, including cutoff frequency ($$f_{T}$$fT), gain–bandwidth product, and transit time ($$\tau τ).

IEEE Transactions on Electron Devices, 2017

Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarit... more Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarity are the major prerequisite conditions of tunnel FETs (TFETs) to make it applicable for Analog/RF circuit applications. Along with that, fabrication of physically doped TFETs is a major concern in device technology. In this context, this paper deals with junctionless TFET with a metal implanted in the oxide at the source/channel and drain/channel junctions to enhance its ON-current and reduce the ambipolar nature. The metal introduced at the source/channel junction generates abruptness and brings improvement in subthreshold slope, which increases the current driving capability of the device. Similarly, the metal implanted at the drain/channel junction widens the energy gap at the same junction to reduce the ambipolar behavior of the device. This also contributes to the enhancement of dc and analog/RF performance of the device. The selection of appropriate work function and length of the metal implanted at both the interfaces is important to maintain the improved ON-current and ambipolarity. This optimization gives idea of keeping the appropriate length, which provides direction toward practical feasibility at the experimental level.

IEEE Transactions on Electron Devices, 2017

A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free bio... more A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept and gate work function engineering. To improve the performance of lateral biosensor (LB), a heavily doped front gate n +-pocket and gate-to-source overlap is introduced in the vertical biosensor (VB). The integrated effect of lateral tunneling as well as vertical tunneling in VB leads to enhanced ON-state current and decrease the subthreshold swing. To evaluate sensing ability of these devices, charged and charged neutral biomolecules are immobilized in nanogap cavity independently. A deep analysis has been performed to show the effect of variation in dielectric constant (k), charge density (ρ), x-composition of Ge, % volume filling of t cavity , length and thickness of a n +-pocket and sensitivity of electrical parameters is also incorporated. Dual-pocket (front and back gate pocket) VB is studied and compared with the LB and VB in the tabular form. Noise characteristic of dielectrically modulated field-effect transistor, L-DMTFET, and V-DMTFET is also evaluated. Index Terms-Band-to-band tunneling (BTBT), dielectrically modulated tunnel field-effect transistor (DMTFET), lateral biosensor (LB), n +-pocket, overlap gate, vertical biosensor (VB). I. INTRODUCTION T HE field-effect transistor (FET)-based biosensors are very popular for label-free detection process and also compatible for the CMOS technology [1]-[4]. FET-based biosensors have some critical challenges such as high subthreshold swing (SS > 60 mV/decade) due to kT/q limit and large response time. This can be eradicated by tunnel FET (TFET)based biosensor as TFET possesses SS <60 mV/decade due to its band-to-band-tunneling (BTBT) mechanism [5]-[7]. Along with this, response time (time required to detect the target biomolecules in the cavity) for TFET-based biosensor is lower because of its lower SS [6]. On this basis, TFET-based Manuscript

Micro & Nano Letters, 2017

This work deals with a distinct concept to realise the junction-less tunnel field effect transist... more This work deals with a distinct concept to realise the junction-less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high-frequency figure of merits. To construct a JL TFET, initially P + silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non-uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to 1 × 10 −14 from 1 × 10 −8 at V gs = −1.5 V. The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around 1 × 10 −21 with little degradation in ON-current. The high work function for the section of drain electrode adjunct to channel provides lower gate-to-drain capacitance (2.67 fF) and superior high-frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog-A model.

Micro & Nano Letters, 2017

The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential cand... more The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential candidate to replace the conventional TFET as it offers fabrication simplicity and its proficiency to be used for ultra-low-power applications. A charge plasma TFET (CPTFET) with hetero materials for enhancement of device performance is presented. For this, a narrow bandgap material (InAs) is used instead of silicon in source region for reducing the lateral tunnelling distance at the source/channel interface. The reduced tunnelling width at the source/ channel junction enables higher band-to-band tunnelling generation rate, thus the device offers higher ON-state current. In this context, a comparative study of CPTFET and hetero junction charge plasma TFET (H-CPTFET) has been performed in terms of transfer characteristic (I ds-V gs), transconductance (g m), gate-to-drain capacitance (C gd), cutoff frequency (f T) and gain-bandwidth product. In addition to this, the effect of variation in channel length (L g) and drain to source voltage (V ds) on the DC and analogue/radio frequency performance of H-CPTFET is also analysed.

2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), 2017

Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for... more Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for the replacement of conventional TFET due to its similar trend in current characteristics and reduced fabrication complexity with low cost. However, the impact of temperature on its performance is yet an undiscovered aspect. The semiconductor devices are known to have significant temperature dependence characteristics. Thus, it is very much of importance to analyse the behavior of the device at different temperature. In this concern, an extensive study has been performed for temperature sensitivity analysis of the behavior of the doping-less TFET. For this, transfer characteristics, energy band diagram and carrier concentration are considered as DC figure of merits, whereas Transconductance (gm), gate-to-drain capacitance (Cgd)), cut off frequency (fT) and gain bandwidth product (GBW) are used as RF performance parameters. Further, the effect of variation in temperature on the Off-state and its components such as Band to Band Tunneling (BTBT), Trap Assisted Tunneling (TAT) and Shockley-Read-Hall (SRH) is also analyzed with different drainchannel spacer widths for doping-less TFET. All the simulations have been performed on Silvaco ATLAS simulator.

A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-p... more A channel-engineered single insulator gate metal oxide field effect transistor (MOSFET) for low-power digital circuitry has been proposed in this study. This study examines the effects of several dielectric insulators used as gate materials, silicon dioxide (SiO2), silicon nitride (Si3N4), hafnium dioxide (HfO2), and zirconium dioxide (ZrO2). The device's performance parameters are enhanced by utilizing different dielectrics in MOSFETs as a gate dielectric since the leakage current is significantly decreased. Following the validation of simulation findings using MOSFET reference data, the structure is evaluated by 15nm and 20nm node technology. In particular 15 nm scale, MOSFET exhibits reduced IOFF, higher ION/IOFF ratio, enhanced Drain Induced Barrier Lowering (DIBL), and Sub-threshold Slope (SS). For proposed MOSFETs, the simulated values of ION, IOFF, ION/IOFF, SS, DIBL, TGF, output conductance (gd), intrinsic gain (Av), and early voltage (VEA) shows improvements which are h...

2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), 2017

Ambipolar conduction is a subject of grave concern for the steep subthreshold slope tunnel field-... more Ambipolar conduction is a subject of grave concern for the steep subthreshold slope tunnel field-effect transistor (TFET) to use it in CMOS circuits. For this, we present a graded channel TFET (GD TFET) to suppress the ambipolar nature of device for wide span of gate to source voltage. Regarding this, half of the channel portion adjacent to source is considered lightly doped whereas, remaining half of the channel portion near to drain is considered heavily doped which modulates the energy bands at the drain channel interface. This leads to disturbance in the abruptness of bands at drain/channel junction resulting into poor band to band tunneling generation rate, hence reduced ambipolar nature of the device is obtained. The device behaviour is compared with the conventional TFET and optimization of heavily doped channel section length is also presented.

2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), 2017

In this paper, investigation for different configurations of N-type Hetero Junction Double Gate T... more In this paper, investigation for different configurations of N-type Hetero Junction Double Gate Tunnel Field-Effect Transistor (HJ-TFET) with Dual metal gate work function and hetero gate dielectric material along with gate underlap is performed to achieve improvements in DC and analog/RF performances. In this regard, the creation of hetero-junction using band gap engineering maintains the lower energy band and higher energy band at source/channel and drain/channel interface respectively to provide high ON current and low ambipolar behavior. A high-density layer of N+ type concentration is added at source/channel junction to obtain abruptness at the same. Further, application of work function engineering on the gate electrode over the channel specified as Tunnel gate (M1) towards the source region and Auxiliary gate (M2) towards the drain region facilitates to achieve higher ON-state current at the cost of poor analog/RF responses. In this concern, hetero gate dielectric and gate under-lap concepts are implied to reduce parasitic capacitances which enhance RF performance of the device. Furthermore, optimization of work function for tunnel gate and the auxiliary gate has been performed to assess the optimum values of work function.

2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), 2017

This manuscript presents a detailed study of Hetero Junction Dual Gate Tunnel Field Effect Transi... more This manuscript presents a detailed study of Hetero Junction Dual Gate Tunnel Field Effect Transistor (HJDG-TFET) for improving the drain current and degrading the ambipolar behavior. The proposed device employs heteromaterial for device analysis. Drain current of the device increases because of narrowing of tunneling barrier width at the sourcechannel junction with the application of low band gap material at the source/channel junction. Hence, the proposed device shows superior performance over conventional DG-TFET in terms of sub threshold slope, drain current, resistant to parasitic capacitance and high frequency parameters. Further, the optimization of channel length and drain voltage is also performed to ensure the reliability of the device. Hence, the overall performance of the HJ-DG-TFET is examined for better efficiency of the device.

IEEE Sensors Journal, 2020

The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-... more The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-2 in terms of spike, envelope and DNA proteins of the virus. The models used in a simulation and the transfer characteristic of the proposed sensor both are first calibrated with the fabricated FET sensor. Than the modification of low workfunction Hf Gate2 (dual metal control gate) has been proposed in the manuscript. The extended Hf Gate2 provides more space for immobilization of the virus proteins and utilize the advantages of charge plasma formation and electrical doping. In the manuscript, sensitivity of the proposed sensor has been investigated by DC and RF parameters in terms of virus proteins and their charge densities. In addition, a comparative analysis of the proposed sensor with and without Hf Gate2 has been examined in terms of DC/RF parameters that reveal a significance of the proposed modification. Moreover, the Impact of replacement of SiO2 insulating layer by HfO2 has also been studied over the sensing ability of sensor in the context of DC/RF components.

Applied Physics A, 2019

In this research, to achieve steep subthreshold slope, high I on ∕I off ratio and low ambipolarit... more In this research, to achieve steep subthreshold slope, high I on ∕I off ratio and low ambipolarity in TFETs, we have proposed a device which consists of metal strips near drain-channel and source-channel interfaces. The proposed device is named as dual metal-strip charge plasma-based junction-less tunnel FET (DMS-CP-JL-TFET), which will improve the device performance in terms of DC and analog/RF figure of merits (FOMs). The introduction of a metal strip near the drain-channel interface which produces a wider energy gap reduces ambipolarity, while the metal strip near the source-channel interface delivers abruptness at the junction, leading to a better subthreshold slope and higher I on ∕I off ratio. Also, positive trap charge (PTC) is taken in the simulations, because the proposed devices have shown great improvement in the presence of PTC, which has also been discussed in this work. In supporting our work, we have added the optimization part for metal strips (M1 and M2) in terms of work functions, lengths to achieve better electrical characteristics.

IEEE Transactions on Electron Devices, 2018

A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP T... more A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p + substrate is taken as silicon film and then metal electrodes with specific work functions are deposited over the silicon film to accumulate n + drain and intrinsic channel regions. This creates abruptness and reduces the barrier at the source/channel interface of CP TFET, which improves the dc characteristics of the device. Furthermore, the drain electrode is separated into two sections and applied with dual work function, which reduces the ambipolar behavior, parasitic capacitance, and enhances radio frequency parameters. The crux of the script is to advance the performance of the device while maintaining the classical CMOS fabrication flow with its inherent advantages by using p + substrate initially. To analyze the performance, a comparison between conventional CP TFET and dual drain electrode CP TFET (proposed) is shown at the simulation level. Optimization of length and workfunction of the section of drain electrode adjacent to the channel is demonstrated to assess the desired ON-current and ambipolarity of the device. Furthermore, the device performance is examined with the application of multigate work function and heterogate dielectric engineering to achieve more improvements in device performance.

Micro & Nano Letters, 2018

In this work, the authors have focused on increasing the current driving capability, speed of ope... more In this work, the authors have focused on increasing the current driving capability, speed of operation, suppression of parasitic capacitance and ambipolarity of the charge plasma tunnel field effect transistor (CPTFET). Gate dielectric and hetero-material engineering are employed in the CPTFET to obtain better drain current. Introduction of high-k dielectric increases the injection of charge carriers in the intrinsic body while a low-energy bandgap III-V material reduces the tunnelling width leading to the increased rate of band-to-band tunnelling of electrons and thus, enhancing the ON-state current of the device. Hence, the proposed device shows superior performance when operated in regime of DC and high frequency. For reducing the ambipolar conduction in the device, a widely used concept of underlapping of gate electrode is employed which reduces the leakage current in the device. Further, to determine the reliability of the device at high frequency, an analysis of linearity parameters is carried out. The proposed device is highly reliable to function at high-frequency regime. Therefore, the overall introduction of gate dielectric engineering, hetero-material engineering and underlapping of gate electrode improves the performance and characteristics of CPTFET.

Microelectronic Engineering, 2018

Applied Physics A, 2018

Ambipolarity in tunnel field-effect transistor (TFET) is a subject of grave concern in the curren... more Ambipolarity in tunnel field-effect transistor (TFET) is a subject of grave concern in the current scenario of the semiconductor industry as this property of device limits its usability in CMOS circuit applications. In this concern, this paper presents a new approach to suppress the ambipolar behavior of dopingless TFET (DL TFET) by controlling the lateral band-to-band tunneling at the drain/channel interface. To execute this, a metal strip is embedded inside the oxide region between gate and drain terminals to modulate the energy bands for preventing the tunneling of charge carriers. The energy bands are widened at the drain-channel junction using this technique and correspondingly ambipolarity is reduced by a factor of 10 11. The variation in the energy bands is examined under different negative gate bias for the proposed device and conventional device which has shown that the energy barrier for the proposed device remains wider for different voltages under the influence of metal embedded. Alignment of the metal strip is varied to obtain the desired performance of the device. In this regard, optimization of work function and length of metal strip along with its position is demonstrated considering its impact on the ambipolar current and ON-state current, which gave 4.0 eV work function and 20 nm as the optimized work function and length of the metal strip, respectively.

Superlattices and Microstructures, 2017

Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET... more Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance, Superlattices and Microstructures (2017),

IEEE Transactions on Electron Devices, 2017

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for ach... more Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current (I on) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving I on , point subthreshold swing and threshold voltage (V th). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

Journal of Computational Electronics, 2017

This paper presents a comparative analysis of the combined effects of gate underlapping and dual ... more This paper presents a comparative analysis of the combined effects of gate underlapping and dual work functionality with hetero gate dielectric engineering for a charge plasma tunnel field-effect transistor (CP TFET). Ultrathin nanoscale devices, despite their size and cost advantage, present serious issues, including doping control, random dopant fluctuation and fabrication complexity. Given these concerns, the concept of charge plasma is introduced to avoid the need for conventional doping for the formation of the source and drain regions, which makes the device resistive to process variation. Conduction for negative gate bias (ambipolarity), excess Miller capacitance (gate-to-drain capacitance) and poor RF performance in TFETs are addressed by the use of gate underlapping from the drain side. In addition, enhanced ON-state current is obtained by work function shifting (dual work functionality). This shift in work function can be accomplished by nitrogen doping of the gate electrode for experimental levels [1]. The combined effects of the underlap and dual work function are seen in the device having a single gate dielectric. However, the ON-state current remains lower in the case of SiO 2 as the gate dielectric. Therefore, a het-B Dharmendra Singh Yadav

Superlattices and Microstructures, 2017

Investigation of gate material engineering in junctionless TFET to overcome the trade-off between... more Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics, Superlattices and Microstructures (2017),

Journal of Computational Electronics, 2017

Achieving steeper subthreshold slope and high ON–OFF current ratio ($$I_{\mathrm{ON}}/I_{\mathrm{... more Achieving steeper subthreshold slope and high ON–OFF current ratio ($$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ION/IOFF) is essential for use of semiconductor devices in switching applications. It is well known that tunnel field-effect transistors face serious issues related to low ON-state current and poor radio frequency (RF) response. We report herein a unique method for realizing a sharp tunneling junction in a charge plasma-based junctionless tunnel field-effect transistor by embedding a metal strip in the oxide region near to the source–channel connection. This modulates the carrier concentration profile at the source–channel interface, making it abrupt. This steeper source–channel tunneling junction results in a reduced tunneling barrier and increased flow of charge carriers at the junction. Furthermore, electron transfer along the channel is accounted for using postprocessing based on the drift–diffusion equations as well as the band-to-band tunneling current. This phenomenon contributes to the improved direct-current (DC) characteristics of the device. Selection of a metal with an appropriate work function for the strip can improve the subthreshold swing and threshold voltage ($$V_{\mathrm{th}}$$Vth) of the device. The increased charge carrier tunneling rate at the junction also results in a huge improvement in RF parameters of the device, including cutoff frequency ($$f_{T}$$fT), gain–bandwidth product, and transit time ($$\tau τ).

IEEE Transactions on Electron Devices, 2017

Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarit... more Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarity are the major prerequisite conditions of tunnel FETs (TFETs) to make it applicable for Analog/RF circuit applications. Along with that, fabrication of physically doped TFETs is a major concern in device technology. In this context, this paper deals with junctionless TFET with a metal implanted in the oxide at the source/channel and drain/channel junctions to enhance its ON-current and reduce the ambipolar nature. The metal introduced at the source/channel junction generates abruptness and brings improvement in subthreshold slope, which increases the current driving capability of the device. Similarly, the metal implanted at the drain/channel junction widens the energy gap at the same junction to reduce the ambipolar behavior of the device. This also contributes to the enhancement of dc and analog/RF performance of the device. The selection of appropriate work function and length of the metal implanted at both the interfaces is important to maintain the improved ON-current and ambipolarity. This optimization gives idea of keeping the appropriate length, which provides direction toward practical feasibility at the experimental level.

IEEE Transactions on Electron Devices, 2017

A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free bio... more A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept and gate work function engineering. To improve the performance of lateral biosensor (LB), a heavily doped front gate n +-pocket and gate-to-source overlap is introduced in the vertical biosensor (VB). The integrated effect of lateral tunneling as well as vertical tunneling in VB leads to enhanced ON-state current and decrease the subthreshold swing. To evaluate sensing ability of these devices, charged and charged neutral biomolecules are immobilized in nanogap cavity independently. A deep analysis has been performed to show the effect of variation in dielectric constant (k), charge density (ρ), x-composition of Ge, % volume filling of t cavity , length and thickness of a n +-pocket and sensitivity of electrical parameters is also incorporated. Dual-pocket (front and back gate pocket) VB is studied and compared with the LB and VB in the tabular form. Noise characteristic of dielectrically modulated field-effect transistor, L-DMTFET, and V-DMTFET is also evaluated. Index Terms-Band-to-band tunneling (BTBT), dielectrically modulated tunnel field-effect transistor (DMTFET), lateral biosensor (LB), n +-pocket, overlap gate, vertical biosensor (VB). I. INTRODUCTION T HE field-effect transistor (FET)-based biosensors are very popular for label-free detection process and also compatible for the CMOS technology [1]-[4]. FET-based biosensors have some critical challenges such as high subthreshold swing (SS > 60 mV/decade) due to kT/q limit and large response time. This can be eradicated by tunnel FET (TFET)based biosensor as TFET possesses SS <60 mV/decade due to its band-to-band-tunneling (BTBT) mechanism [5]-[7]. Along with this, response time (time required to detect the target biomolecules in the cavity) for TFET-based biosensor is lower because of its lower SS [6]. On this basis, TFET-based Manuscript

Micro & Nano Letters, 2017

This work deals with a distinct concept to realise the junction-less tunnel field effect transist... more This work deals with a distinct concept to realise the junction-less tunnel field effect transistor (JL TFET) by creating the plasma of charges. The crux of this study is to reduce ambipolar conduction and to improve high-frequency figure of merits. To construct a JL TFET, initially P + silicon film is considered and then metal electrodes are used to form drain and channel region. The drain electrode is separated into two sections and the work function of section adjacent to channel is selected higher than the other section. This provides a non-uniform doping profile in the drain region creating large barrier at the drain/channel junction to prevent the ambipolar conduction. Ambipolarity is reduced to 1 × 10 −14 from 1 × 10 −8 at V gs = −1.5 V. The selection of work function and length of drain electrode adjunct to channel is crucial for optimising device performance. This optimisation provides information that work function >4.0 eV and length = 10 nm completely suppresses the ambipolarity which is around 1 × 10 −21 with little degradation in ON-current. The high work function for the section of drain electrode adjunct to channel provides lower gate-to-drain capacitance (2.67 fF) and superior high-frequency responses. Furthermore, performance assessment at circuit level is done by implementing primary digital circuits as inverter and NAND logic with lookup table based Verilog-A model.

Micro & Nano Letters, 2017

The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential cand... more The charge plasma-based tunnel field-effect transistor (TFET) has been seen as the potential candidate to replace the conventional TFET as it offers fabrication simplicity and its proficiency to be used for ultra-low-power applications. A charge plasma TFET (CPTFET) with hetero materials for enhancement of device performance is presented. For this, a narrow bandgap material (InAs) is used instead of silicon in source region for reducing the lateral tunnelling distance at the source/channel interface. The reduced tunnelling width at the source/ channel junction enables higher band-to-band tunnelling generation rate, thus the device offers higher ON-state current. In this context, a comparative study of CPTFET and hetero junction charge plasma TFET (H-CPTFET) has been performed in terms of transfer characteristic (I ds-V gs), transconductance (g m), gate-to-drain capacitance (C gd), cutoff frequency (f T) and gain-bandwidth product. In addition to this, the effect of variation in channel length (L g) and drain to source voltage (V ds) on the DC and analogue/radio frequency performance of H-CPTFET is also analysed.

2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC), 2017

Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for... more Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for the replacement of conventional TFET due to its similar trend in current characteristics and reduced fabrication complexity with low cost. However, the impact of temperature on its performance is yet an undiscovered aspect. The semiconductor devices are known to have significant temperature dependence characteristics. Thus, it is very much of importance to analyse the behavior of the device at different temperature. In this concern, an extensive study has been performed for temperature sensitivity analysis of the behavior of the doping-less TFET. For this, transfer characteristics, energy band diagram and carrier concentration are considered as DC figure of merits, whereas Transconductance (gm), gate-to-drain capacitance (Cgd)), cut off frequency (fT) and gain bandwidth product (GBW) are used as RF performance parameters. Further, the effect of variation in temperature on the Off-state and its components such as Band to Band Tunneling (BTBT), Trap Assisted Tunneling (TAT) and Shockley-Read-Hall (SRH) is also analyzed with different drainchannel spacer widths for doping-less TFET. All the simulations have been performed on Silvaco ATLAS simulator.