Tsutomu Sasao - Academia.edu (original) (raw)

Papers by Tsutomu Sasao

2015 IEEE International Symposium on Multiple-Valued Logic, 2015

This paper proposes a new reduction rule for edge-valued multi-valued decision diagrams (EVMDDs),... more This paper proposes a new reduction rule for edge-valued multi-valued decision diagrams (EVMDDs), which improves the speed of analysis of multi-state systems (MSSs). Existing reduction rules for decision diagrams remove redundant nodes, while the proposed rule removes redundant edges in EVMDDs. Since the time to do an analysis in an MSS depends on the number of edges in the EVMDD, the proposed rule is faster especially when used with edge minimization algorithms based on variable grouping. Experimental results show that the proposed rule reduces the number of edges by up to 30%, and this results in an analysis time that is reduced by up to 30%.

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159)

We present a method of path selection and test generation for path delay faults. The proposed met... more We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-s... more Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper proposes a novel soft-error tolerant TCAM for multiplebit-flip errors using partial don't-care keys (X-keys), called k-TX. k-TX corrects up to k-bit flip errors and significantly enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. k-TX consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and an ECC-SRAM. First, k-TX randomly selects a search key. After that, k-TX detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and k-TX refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of k-TX outperforms other schemes significantly. Moreover, the hardware overhead of k-TX is small due to the use of only a single TCAM. k-TX can be easily implemented and is useful for fault-tolerant packet classifiers.

Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94)

In this paper we eztend the method for the calculation of Walsh transform of binary switching fun... more In this paper we eztend the method for the calculation of Walsh transform of binary switching functions through the binary decision diagrams to the calculation of Reed-Muller-Fourier transform of p-valued through multiple-place decision diagrams functions through multiple-place decision diagrams. The calculation of Reed-Muller coeficients of binary switching functions is involved as a special case for p = 2.

IEICE Transactions on Information and Systems, 2017

Index generation functions model content-addressable memory, and are useful in virus detectors an... more Index generation functions model content-addressable memory, and are useful in virus detectors and routers. Linear decompositions yield simpler circuits that realize index generation functions. This paper proposes a balanced decision tree based heuristic to efficiently design linear decompositions for index generation functions. The proposed heuristic finds a good linear decomposition of an index generation function by using appropriate cost functions and a constraint to construct a balanced tree. Since the proposed heuristic is fast and requires a small amount of memory, it is applicable even to large index generation functions that cannot be solved in a reasonable time by existing heuristics. This paper shows time and space complexities of the proposed heuristic, and experimental results using some large examples to show its efficiency.

2013 IEEE 7th International Symposium on Embedded Multicore Socs, 2013

ABSTRACT A decision diagram machine (DDM) is a special-purpose processor that uses special instru... more ABSTRACT A decision diagram machine (DDM) is a special-purpose processor that uses special instructions to evaluate a decision diagram. This paper presents a packet classifier using a parallel edge-valued multi-valued decision diagram (EVMDD (k)) machine. To reduce computation time and code size, first, a rule set for the packet classifier is partitioned into groups. Then, the parallel EVMDD (k) machine evaluates them. We implemented the parallel EVMDD (k) machine consisting of 32 EVMDD (4) machines on an FPGA, and compared it with the Intel's Core i5 microprocessor running at 1.7GHz. Our machine is 7.8-40.1 times faster than the Core i5, and it requires only 12.0-52.6 percents of the memory for the Core~i5.

In this paper, we show a method to locate a single stuckat fault of a random access memory (RAM).... more In this paper, we show a method to locate a single stuckat fault of a random access memory (RAM). From the fail-bitmaps of the RAM, we obtain their Walsh spectrum. For a single stuck-at fault, we show that the fault can be identified and located by using only the 0-th and 1-st coefficients of the spectrum. We also show a circuit to compute these coefficients. The computation time is O(2 n), where n is the number of bits in the address of the RAM. The computation time is much shorter than one that uses a logic minimization method.

Automation and Remote Control

This paper shows that binary decision diagrams (BDDs) and their generalizations are not only repr... more This paper shows that binary decision diagrams (BDDs) and their generalizations are not only representations of switching and integer-valued functions, but also Fourier-like series expansions of them. Furthermore, it shows that edge-valued binary decision diagrams (EVBDDs) are related to arithmetic transform decision diagrams (ACDDs), which are the integer counterparts of the functional decision diagrams (FDDs). Finally, it shows that the complexity of multi-terminal binary decision diagrams (MTBDDs), EVBDDs and ACDDs of a function f depends on the structure of the truth-vector of f , partial arithmetic transform spectra of f and the arithmetic transform spectrum of f , respectively.

Proceedings of 1998 Asia and South Pacific Design Automation Conference

This paper classies dierent decision diagrams (DDs) for discrete functions with respect to the do... more This paper classies dierent decision diagrams (DDs) for discrete functions with respect to the domain and range of represented functions. Relationships among dierent DDs and their relations to spectral transforms are also shown. That provides a unied interpretation of DDs, and their further classication with respect to the spectral transforms.

2014 IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Given an incompletely specified index generation function, the number of variables to represent t... more Given an incompletely specified index generation function, the number of variables to represent the function can often be reduced by properly assigning don't care values. In this paper, we derive a lower bound on the number of variables necessary to represent a given incompletely specified index generation function. We also derive three properties of incompletely specified index generation functions. We confirm these properties by experiments using random index generation functions.

Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005

[1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2014

This paper shows a method to represent interval functions by using head-tail expressions. The hea... more This paper shows a method to represent interval functions by using head-tail expressions. The head-tail expressions represent greaterthan GT (X : A) functions, less-than LT (X : B) functions, and interval functions IN 0 (X : A, B) more efficiently than sum-of-products expressions. Let n be the number of bits to represent the largest value in the interval (A, B). This paper proves that a head-tail expression (HT) represents an interval function with at most n words in a ternary content addressable memory (TCAM) realization. It also shows the average numbers of factors to represent interval functions by HTs for up to n = 16, which were obtained by a computer simulation. It also conjectures that, for sufficiently large n, the average number of factors to represent n-variable interval functions by HTs is at most 2 3 n − 5 9. Experimental results also show that, for n ≥ 10, to represent interval functions, HTs require at least 20% fewer factors than MSOPs, on the average.

2012 IEEE Computer Society Annual Symposium on VLSI, 2012

This paper presents a method to generate head-tail expressions for Ternary Content Addressable Me... more This paper presents a method to generate head-tail expressions for Ternary Content Addressable Memories (TCAMs). First, we derive head-tail expressions for interval functions. We introduce a fast prefix sum-of-product (PreSOP) generator (FP) which generates products using the bit patterns of the endpoints. Next, we propose a direct head-tail expression generator (DHT). Experimental results show that DHT generates much smaller TCAM than FP. The proposed algorithm is useful for simplified TCAM generator for packet classification.

2013 IEEE 31st International Conference on Computer Design (ICCD), 2013

In the internet, packets are classified by source and destination addresses and ports, as well as... more In the internet, packets are classified by source and destination addresses and ports, as well as protocol type. Ternary content addressable memories (TCAMs) are often used to perform this operation. This paper shows a method to reduce the number of words in TCAM for multi-field classification functions. We use head-tail expressions to represent a multi-field classification rule. Furthermore, we present an O(r 2)-algorithm, called MFHT, to generate simplified TCAMs for two-field classification functions, where r is the number of rules. Experimental results show that MFHT achieves a 58% reduction of words for random rules and a 52% reduction of words for ACL and FW rules. Moreover, MFHT is fast and useful for simplifying TCAM for packet classification.

Memory-Based Logic Synthesis, 2011

Given a set of k distinct binary vectors of n bits, for each vector assign a unique integer from ... more Given a set of k distinct binary vectors of n bits, for each vector assign a unique integer from 1 to k. An incompletely specified index generation function produces an index for a given vector. This tutorial first introduces index generation functions, which are useful for pattern matching in communication circuits. Then, it shows a method to represent a given index generation function using fewer variables. A linear transformation is used to reduce the number of variables. An extension to the multiple-valued case is also presented. 1 INDEX GENERATION FUNCTION This tutorial shows recent results on index generation functions. Applications of index generation functions include: IP address table lookup, packet filtering, terminal access controllers, memory patch circuits, virus scan circuits, fault maps for memory, and pattern matching. In addition, this paper introduces an index generation unit that efficiently realizes an index generation function by a linear circuit and a pair of smaller memories. Due to space limitations, definitions of standard terminology used in switching circuit theory [10] are omitted. Definition 1. Consider a set of k different binary vectors of n bits. These vectors are registered vectors. For each registered vector, assign a unique integer from 1 to k. A registered vector table shows the index of each registered vector. An index generation function produces the corresponding index if the input matches a registered vector, and produces 0 otherwise. Let 1 330i-MVLSC˙V2 1 2 APPLICATIONS An index generator is a circuit that realizes an index generation function. Index generators are used for address tables in the internet, terminal access controllers for local area networks, databases, memory patch circuits, electronic dictionaries, password lists, code converters etc. [12]. 2.1 Address Table in the Internet IP addresses of the internet are often represented in 32 bits. An address table for a router stores IP addresses and corresponding indexes to a memory 330i-MVLSC˙V2 2 INDEX GENERATION FUNCTIONS 3 FIGURE 1 Terminal access controller. that stores the details of the addresses. For example, in a typical problem, the number of addresses in the table is 40, 000. Thus, the number of inputs is 32 and the number of outputs is 16, which can represent 65,536 addresses. Note that the address table must be updated frequently. 2.2 Terminal Access Controller A terminal access controller (TAC) for a local area network checks whether the requested terminal has permission to access Web resources outside the local area network, E-mail, FTP, Telnet, etc.. In Figure 1, eight terminals are connected to the TAC. Some can access all the resources. Others can access only limited resources because of security risks. The TAC checks whether the requested computer has permission to access the Web, E-mail, FTP, Telnet, or not. Each terminal has its unique MAC address represented by 48 bits. We assume that the number of terminals in the table is at most 255. To implement the TAC, we use an index generator and a memory. The memory stores the details of the terminals. The number of inputs for the index generator is 48 and the number of outputs is 8. In many cases, the table for the terminal access controller must be updated frequently. Example 2. Figure 2 shows an example of the terminal access controller.

Proceedings Sixth Asian Test Symposium (ATS'97)

This paper considers two types of n-bit adders, ripple carry adders and cascaded carry lookahead ... more This paper considers two types of n-bit adders, ripple carry adders and cascaded carry lookahead adders, with minimum tests for stuck-at fault models. In the first part, we present two types of full adders consisting of five gates, and show their minimality: the adders contains the minimum number of gates among adders consisting of only 2-input gates. We also prove that one of the full adders can be tested by only three test patterns for single stuck-at faults. We also present two types of 4-bit carry look-ahead adders, and prove that the sizes of the minimum tests are 10 and 12 for single stuck-at faults. In the second part, we consider the tests for the cascaded adders and show the followings: Single stuck-at faults in an n-bit ripple carry adder can be detected by the same size of tests as those of a full adder, and six tests are sufficient even for multiple stuck-at faults. For the 4m-bit cascaded carry look-ahead adders, the sizes of the minimum tests are less than 12 for single stuck-at faults. Note that the sizes of the minimal tests do not depend onthe value of n nor m. These tests are considerably smaller than previously published ones.

The Kluwer International Series in Engineering and Computer Science, 1993

This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization an... more This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the packet assembler and the regular expression matching are implemented by the dedicated hardware. On the other hand, the counting of matching results and the system control are implemented by a microprocessor. A regular expression matching circuit is performed as follows: First, the given regular expressions are converted into a non-deterministic finite automaton (NFA). Then, to reduce the number of states, the NFA is converted to a modular non-deterministic finite automaton (MNFA(p)) with p-character-consuming transition. Finally, a finite-input memory machine (FIMM) to detect p-characters is generated, and the matching elements (MEs) realizing the states for the MNFA(p) are generated. We loaded 140 regular expressions of the MEMOCODE 2010 design contest on Terasic Corp. DE3 prototyping board (FPGA: Altera's Strati...

Contents: 1. Overview of Neural Networks 2. Fundamentals of Neural Networks 3. Feedforward Neural... more Contents: 1. Overview of Neural Networks 2. Fundamentals of Neural Networks 3. Feedforward Neural Networks 4. Neural Networks Architectures 5. Associative Memories 6. Introduction to Fuzzy Sets: Basic Definitions and Relations 7. Introduction to Fuzzy Logic 8. Fuzzy Control and Stability 8A. Advanced Process Control 8B. Fuzzy Logic Application 2011 284 pp 9789381075401 BSPBSP PB Rs. 250.00